57 lines
2.3 KiB
Plaintext
57 lines
2.3 KiB
Plaintext
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* Renesas CPG Module Stop (MSTP) Clocks
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The CPG can gate SoC device clocks. The gates are organized in groups of up to
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32 gates.
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This device tree binding describes a single 32 gate clocks group per node.
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Clocks are referenced by user nodes by the MSTP node phandle and the clock
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index in the group, from 0 to 31.
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Required Properties:
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- compatible: Must be one of the following
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- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
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- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
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- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
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- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
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- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
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- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
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- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
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- "renesas,cpg-mstp-clock" for generic MSTP gate clocks
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- reg: Base address and length of the I/O mapped registers used by the MSTP
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clocks. The first register is the clock control register and is mandatory.
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The second register is the clock status register and is optional when not
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implemented in hardware.
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- clocks: Reference to the parent clocks, one per output clock. The parents
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must appear in the same order as the output clocks.
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- #clock-cells: Must be 1
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- clock-output-names: The name of the clocks as free-form strings
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- renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
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The clocks, clock-output-names and renesas,clock-indices properties contain one
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entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
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gate clocks must not be declared.
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Example
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-------
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#include <dt-bindings/clock/r8a7790-clock.h>
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mstp3_clks: mstp3_clks@e615013c {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
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clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
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<&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
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<&mmc0_clk>;
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#clock-cells = <1>;
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clock-output-names =
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"tpu0", "mmcif1", "sdhi3", "sdhi2",
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"sdhi1", "sdhi0", "mmcif0";
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clock-indices = <
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R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
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R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
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R8A7790_CLK_MMCIF0
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>;
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};
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