35 lines
1.3 KiB
Plaintext
35 lines
1.3 KiB
Plaintext
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* ARM Cortex A53 / A57 cache error reporting driver
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Required properties:
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- compatible: Should be "arm,arm64-cpu-erp"
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- interrupts: List of hardware interrupts that may indicate an error condition
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in the CPU subsystem, or in the L1 / L2 caches. At least one interrupt entry
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is required.
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- interrupt-names: Must contain one or more of the following IRQ types:
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"pri-dbe-irq" - double-bit error interrupt for primary cluster
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"sec-dbe-irq" - double-bit error interrupt for secondary cluster
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"pri-ext-irq" - external bus error interrupt for primary cluster
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"sec-ext-irq" - external bus error interrupt for secondary cluster
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"cci-irq" - CCI error interrupt. If this property is present, having
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the 'cci' reg-base defined using the 'reg' property is
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recommended.
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At least one irq entry is required.
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Optional properties:
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- reg: Should contain physical address of the CCI register space
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- reg-names: Should contain 'cci'. Must be present if 'reg' property is present
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- poll-delay-msec: Indicates how often the edac check callback should be called. Time in msec.
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Example:
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cpu_cache_erp {
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compatible = "arm,arm64-cpu-erp";
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interrupt-names = "pri-dbe-irq",
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"sec-dbe-irq",
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"pri-ext-irq",
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"sec-ext-irq";
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interrupts = <0 92 0>,
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<0 91 0>,
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<0 96 0>,
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<0 95 0>;
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};
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