21 lines
479 B
Plaintext
21 lines
479 B
Plaintext
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L2 Cache Clock Controller
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The L2 Cache Clock Controller provides clock, power domain, and
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reset control to a L2-cache for a cluster. There is L2CCC register
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region per CPU Cluster.
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Required properties:
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- compatible: Can be one of:
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"qcom,8916-l2ccc"
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"qcom,titanium-l2ccc"
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"qcom,8937-l2ccc"
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- reg: This specifies the base address and size of
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the register region.
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Example:
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clock-controller@f900f000 {
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compatible = "qcom,8916-l2ccc"";
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reg = <0xf900f000 0x1000>;
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}
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