46 lines
1.7 KiB
Plaintext
46 lines
1.7 KiB
Plaintext
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* Qualcomm Application CPU clock driver
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clock-a7 is the driver for the Root Clock Generator (rcg) hw which controls
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the cpu rate. RCGs support selecting one of several clock inputs, as well as
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a configurable divider. This hw is different than normal rcgs in that it may
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optionally have a register which encodes the maximum rate supported by hw.
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Required properties:
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- compatible: "qcom,clock-a7-8226", "qcom,clock-a7-9630",
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"qcom,clock-a53-8916", "qcom,clock-a7-vpipa",
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"qcom,clock-a7-9640", "qcom,clock-a7-californium"
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"qcom,clock-a7-9640", "qcom,clock-a7-mdm9607"
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- reg: pairs of physical address and region size
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- reg-names: "rcg-base" is expected
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- clock-names: list of names of clock inputs
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- qcom,speedX-bin-vZ:
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A table of CPU frequency (Hz) to regulator voltage (uV) mapping.
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Format: <freq uV>
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This represents the max frequency possible for each possible
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power configuration for a CPU that's binned as speed bin X,
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speed bin revision Z. Speed bin values can be between [0-7]
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and the version can be between [0-3].
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- cpu-vdd-supply: regulator phandle for cpu power domain.
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Optional properties:
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- reg-names: "efuse", "efuse1"
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- qcom,safe-freq: Frequency in HZ
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When switching rates from A to B, the mux div clock will
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instead switch from A -> safe_freq -> B.
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- qcom,enable-opp: This will allow to register the cpu clock with OPP
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framework.
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Example:
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qcom,acpuclk@f9011050 {
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compatible = "qcom,clock-a7-8226";
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reg = <0xf9011050 0x8>;
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reg-names = "rcg_base";
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cpu-vdd-supply = <&apc_vreg_corner>;
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clock-names = "clk-4", "clk-5";
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qcom,speed0-bin-v0 =
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<384000000 1150000>,
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<600000000 1200000>;
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};
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