539 lines
12 KiB
C
539 lines
12 KiB
C
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/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <platform/iomap.h>
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#include <platform/irqs.h>
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#include <platform/gpio.h>
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#include <reg.h>
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#include <target.h>
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#include <platform.h>
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#include <dload_util.h>
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#include <uart_dm.h>
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#include <mmc.h>
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#include <spmi.h>
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#include <board.h>
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#include <smem.h>
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#include <baseband.h>
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#include <dev/keys.h>
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#include <crypto5_wrapper.h>
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#include <hsusb.h>
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#include <clock.h>
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#include <partition_parser.h>
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#include <scm.h>
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#include <platform/clock.h>
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#include <platform/gpio.h>
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#include <platform/timer.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sdhci_msm.h>
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extern bool target_use_signed_kernel(void);
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static void set_sdc_power_ctrl();
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static unsigned int target_id;
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#if MMC_SDHCI_SUPPORT
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struct mmc_device *dev;
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#endif
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#define PMIC_ARB_CHANNEL_NUM 0
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#define PMIC_ARB_OWNER_ID 0
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#define WDOG_DEBUG_DISABLE_BIT 17
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#define CE_INSTANCE 2
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#define CE_EE 1
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#define CE_FIFO_SIZE 64
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#define CE_READ_PIPE 3
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#define CE_WRITE_PIPE 2
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#define CE_READ_PIPE_LOCK_GRP 0
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#define CE_WRITE_PIPE_LOCK_GRP 0
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#define CE_ARRAY_SIZE 20
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#define FASTBOOT_MODE 0x77665500
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#define BOARD_SOC_VERSION1(soc_rev) (soc_rev >= 0x10000 && soc_rev < 0x20000)
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#if MMC_SDHCI_SUPPORT
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static uint32_t mmc_sdhci_base[] =
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{ MSM_SDC1_SDHCI_BASE };
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static uint32_t mmc_sdc_pwrctl_irq[] =
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{ SDCC1_PWRCTL_IRQ };
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#endif
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static uint32_t mmc_sdc_base[] =
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{ MSM_SDC1_BASE };
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void target_early_init(void)
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{
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#if WITH_DEBUG_UART
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uart_dm_init(3, 0, BLSP1_UART3_BASE);
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#endif
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}
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/* Return 1 if vol_up pressed */
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static int target_volume_up()
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{
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return 0;
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}
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/* Return 1 if vol_down pressed */
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uint32_t target_volume_down()
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{
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return 0;
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}
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static void target_keystatus()
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{
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keys_init();
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if (target_volume_down())
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keys_post_event(KEY_VOLUMEDOWN, 1);
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if (target_volume_up())
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keys_post_event(KEY_VOLUMEUP, 1);
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}
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/* Set up params for h/w CE. */
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void target_crypto_init_params()
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{
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struct crypto_init_params ce_params;
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/* Set up base addresses and instance. */
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ce_params.crypto_instance = CE_INSTANCE;
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ce_params.crypto_base = MSM_CE2_BASE;
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ce_params.bam_base = MSM_CE2_BAM_BASE;
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/* Set up BAM config. */
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ce_params.bam_ee = CE_EE;
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ce_params.pipes.read_pipe = CE_READ_PIPE;
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ce_params.pipes.write_pipe = CE_WRITE_PIPE;
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ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
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ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
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/* Assign buffer sizes. */
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ce_params.num_ce = CE_ARRAY_SIZE;
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ce_params.read_fifo_size = CE_FIFO_SIZE;
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ce_params.write_fifo_size = CE_FIFO_SIZE;
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/* BAM is initialized by TZ for this platform.
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* Do not do it again as the initialization address space
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* is locked.
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*/
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ce_params.do_bam_init = 0;
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crypto_init_params(&ce_params);
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}
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crypto_engine_type board_ce_type(void)
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{
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return CRYPTO_ENGINE_TYPE_HW;
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}
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#if MMC_SDHCI_SUPPORT
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static void target_mmc_sdhci_init()
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{
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static uint32_t mmc_clks[] = {
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MMC_CLK_200MHZ, MMC_CLK_96MHZ, MMC_CLK_50MHZ };
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struct mmc_config_data config;
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unsigned int i;
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memset(&config, 0, sizeof config);
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config.bus_width = DATA_BUS_WIDTH_8BIT;
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/* Trying Slot 1*/
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config.slot = 1;
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config.sdhc_base = mmc_sdhci_base[config.slot - 1];
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config.pwrctl_base = mmc_sdc_base[config.slot - 1];
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config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
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config.hs400_support = 0;
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for (i = 0; i < ARRAY_SIZE(mmc_clks); ++i) {
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config.max_clk_rate = mmc_clks[i];
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dprintf(INFO, "SDHC Running at %u MHz\n",
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config.max_clk_rate / 1000000);
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dev = mmc_init(&config);
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if (dev && partition_read_table() == 0)
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return;
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}
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if (dev == NULL)
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dprintf(CRITICAL, "mmc init failed!");
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else
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dprintf(CRITICAL, "Error reading the partition table info\n");
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ASSERT(0);
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}
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void *target_mmc_device()
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{
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return (void *) dev;
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}
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#else
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static void target_mmc_mci_init()
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{
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uint32_t base_addr;
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uint8_t slot;
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/* Trying Slot 1 */
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slot = 1;
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base_addr = mmc_sdc_base[slot - 1];
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if (mmc_boot_main(slot, base_addr))
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{
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dprintf(CRITICAL, "mmc init failed!");
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ASSERT(0);
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}
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}
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/*
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* Function to set the capabilities for the host
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*/
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void target_mmc_caps(struct mmc_host *host)
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{
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host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
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host->caps.ddr_mode = 0;
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host->caps.hs200_mode = 1;
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host->caps.hs_clk_rate = MMC_CLK_96MHZ;
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}
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#endif
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void target_init(void)
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{
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dprintf(INFO, "target_init()\n");
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target_keystatus();
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if (target_use_signed_kernel())
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target_crypto_init_params();
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/*
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* Set drive strength & pull ctrl for
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* emmc
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*/
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set_sdc_power_ctrl();
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#if MMC_SDHCI_SUPPORT
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target_mmc_sdhci_init();
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#else
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target_mmc_mci_init();
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#endif
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}
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unsigned board_machtype(void)
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{
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return target_id;
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}
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void target_fastboot_init(void)
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{
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}
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/* Detect the target type */
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void target_detect(struct board_data *board)
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{
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/* This property is filled as part of board.c */
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}
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/* Detect the modem type */
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void target_baseband_detect(struct board_data *board)
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{
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uint32_t platform;
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uint32_t platform_subtype;
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platform = board->platform;
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platform_subtype = board->platform_subtype;
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/*
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* Look for platform subtype if present, else
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* check for platform type to decide on the
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* baseband type
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*/
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switch (platform_subtype) {
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case HW_PLATFORM_SUBTYPE_UNKNOWN:
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break;
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default:
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dprintf(CRITICAL, "Platform Subtype : %u is not supported\n",platform_subtype);
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ASSERT(0);
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};
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switch (platform) {
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case FSM9008:
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case FSM9010:
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case FSM9016:
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case FSM9055:
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board->baseband = BASEBAND_MSM;
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break;
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default:
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dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
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ASSERT(0);
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};
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}
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unsigned target_baseband()
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{
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return board_baseband();
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}
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void target_serialno(unsigned char *buf)
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{
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unsigned int serialno;
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if (target_is_emmc_boot()) {
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serialno = mmc_get_psn();
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snprintf((char *)buf, 13, "%x", serialno);
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}
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}
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unsigned check_reboot_mode(void)
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{
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uint32_t restart_reason = 0;
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uint32_t restart_reason_addr;
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restart_reason_addr = RESTART_REASON_ADDR_V2;
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/* Read reboot reason and scrub it */
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restart_reason = readl(restart_reason_addr);
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writel(0x00, restart_reason_addr);
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return restart_reason;
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}
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void reboot_device(unsigned reboot_reason)
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{
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/* Write the reboot reason */
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writel(reboot_reason, RESTART_REASON_ADDR_V2);
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/* Disable Watchdog Debug.
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* Required becuase of a H/W bug which causes the system to
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* reset partially even for non watchdog resets.
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*/
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writel(readl(GCC_WDOG_DEBUG) & ~(1 << WDOG_DEBUG_DISABLE_BIT), GCC_WDOG_DEBUG);
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dsb();
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/* Wait until the write takes effect. */
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while(readl(GCC_WDOG_DEBUG) & (1 << WDOG_DEBUG_DISABLE_BIT));
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/* Drop PS_HOLD for MSM */
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writel(0x00, MPM2_MPM_PS_HOLD);
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mdelay(5000);
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dprintf(CRITICAL, "Rebooting failed\n");
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}
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int set_download_mode(enum dload_mode mode)
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{
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dload_util_write_cookie(mode == NORMAL_DLOAD ?
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DLOAD_MODE_ADDR_V2 : EMERGENCY_DLOAD_MODE_ADDR_V2, mode);
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return 0;
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}
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/* Returns 1 if target supports continuous splash screen. */
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int target_cont_splash_screen()
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{
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return 0;
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}
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unsigned target_pause_for_battery_charge(void)
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{
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return 0;
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}
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void target_uninit(void)
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{
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#if MMC_SDHCI_SUPPORT
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mmc_put_card_to_sleep(dev);
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sdhci_mode_disable(&dev->host);
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#else
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mmc_put_card_to_sleep();
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#endif
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}
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void shutdown_device()
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{
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dprintf(CRITICAL, "Going down for shutdown.\n");
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/* Drop PS_HOLD for MSM */
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writel(0x00, MPM2_MPM_PS_HOLD);
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mdelay(5000);
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dprintf(CRITICAL, "Shutdown failed\n");
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}
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|
|
static void set_sdc_power_ctrl()
|
||
|
|
{
|
||
|
|
/* Drive strength configs for sdc pins */
|
||
|
|
struct tlmm_cfgs sdc1_hdrv_cfg[] =
|
||
|
|
{
|
||
|
|
{
|
||
|
|
off: SDC1_CLK_HDRV_CTL_OFF,
|
||
|
|
val: TLMM_CUR_VAL_10MA,
|
||
|
|
mask: TLMM_HDRV_MASK
|
||
|
|
},
|
||
|
|
{
|
||
|
|
off: SDC1_CMD_HDRV_CTL_OFF,
|
||
|
|
val: TLMM_CUR_VAL_10MA,
|
||
|
|
mask: TLMM_HDRV_MASK
|
||
|
|
},
|
||
|
|
{
|
||
|
|
off: SDC1_DATA_HDRV_CTL_OFF,
|
||
|
|
val: TLMM_CUR_VAL_10MA,
|
||
|
|
mask: TLMM_HDRV_MASK
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Pull configs for sdc pins */
|
||
|
|
struct tlmm_cfgs sdc1_pull_cfg[] =
|
||
|
|
{
|
||
|
|
{
|
||
|
|
off: SDC1_CLK_PULL_CTL_OFF,
|
||
|
|
val: TLMM_NO_PULL,
|
||
|
|
mask: TLMM_PULL_MASK
|
||
|
|
},
|
||
|
|
{
|
||
|
|
off: SDC1_CMD_PULL_CTL_OFF,
|
||
|
|
val: TLMM_PULL_UP,
|
||
|
|
mask: TLMM_PULL_MASK
|
||
|
|
},
|
||
|
|
{
|
||
|
|
off: SDC1_DATA_PULL_CTL_OFF,
|
||
|
|
val: TLMM_PULL_UP,
|
||
|
|
mask: TLMM_PULL_MASK
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Set the drive strength & pull control values */
|
||
|
|
tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
|
||
|
|
tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
|
||
|
|
}
|
||
|
|
|
||
|
|
int emmc_recovery_init(void)
|
||
|
|
{
|
||
|
|
extern int _emmc_recovery_init(void);
|
||
|
|
|
||
|
|
return _emmc_recovery_init();
|
||
|
|
}
|
||
|
|
|
||
|
|
#define USB30_QSCRATCH_GENERAL_CFG (MSM_USB30_QSCRATCH_BASE + 0x08)
|
||
|
|
#define USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_SEL (1 << 0)
|
||
|
|
#define USB30_QSCRATCH_GENERAL_CFG_PIPE3_PHYSTATUS_SW (1 << 3)
|
||
|
|
#define USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_DIS (1 << 8)
|
||
|
|
|
||
|
|
#define CM_DWC_USB2_USB_PHY_UTMI_CTRL5 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0x74)
|
||
|
|
#define CM_DWC_USB2_USB_PHY_HS_PHY_CTRL_COMMON0 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0x78)
|
||
|
|
#define CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X0 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0x98)
|
||
|
|
#define CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X1 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0x9c)
|
||
|
|
#define CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X2 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0xa0)
|
||
|
|
#define CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X3 (CM_DWC_USB2_CM_DWC_USB2_BASE + 0xa4)
|
||
|
|
#define CM_DWC_USB2_USB_PHY_REFCLK_CTRL (CM_DWC_USB2_CM_DWC_USB2_BASE + 0xe8)
|
||
|
|
|
||
|
|
void target_usb_phy_mux_configure(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
void target_usb_phy_init(void)
|
||
|
|
{
|
||
|
|
uint32_t val;
|
||
|
|
|
||
|
|
/* Disable clock */
|
||
|
|
val = readl(USB30_QSCRATCH_GENERAL_CFG);
|
||
|
|
val |= USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_DIS;
|
||
|
|
writel(val, USB30_QSCRATCH_GENERAL_CFG);
|
||
|
|
mdelay(1);
|
||
|
|
|
||
|
|
/* Select UTMI instead of PIPE3 */
|
||
|
|
val |= USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_SEL;
|
||
|
|
writel(val, USB30_QSCRATCH_GENERAL_CFG);
|
||
|
|
val |= USB30_QSCRATCH_GENERAL_CFG_PIPE3_PHYSTATUS_SW;
|
||
|
|
writel(val, USB30_QSCRATCH_GENERAL_CFG);
|
||
|
|
mdelay(1);
|
||
|
|
|
||
|
|
/* Enable clock */
|
||
|
|
val &= ~USB30_QSCRATCH_GENERAL_CFG_PIPE_UTMI_CLK_DIS;
|
||
|
|
writel(val, USB30_QSCRATCH_GENERAL_CFG);
|
||
|
|
|
||
|
|
/* Initialize HS PICO PHY */
|
||
|
|
writel(0xc4, CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X0);
|
||
|
|
writel(0x88, CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X1);
|
||
|
|
writel(0x11, CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X2);
|
||
|
|
writel(0x03, CM_DWC_USB2_USB_PHY_PARAMETER_OVERRIDE_X3);
|
||
|
|
|
||
|
|
writel(0x02, CM_DWC_USB2_USB_PHY_UTMI_CTRL5);
|
||
|
|
mdelay(1);
|
||
|
|
writel(0x00, CM_DWC_USB2_USB_PHY_UTMI_CTRL5);
|
||
|
|
|
||
|
|
val = readl(CM_DWC_USB2_USB_PHY_REFCLK_CTRL);
|
||
|
|
val &= ~(7 << 1);
|
||
|
|
val |= (6 << 1);
|
||
|
|
writel(val, CM_DWC_USB2_USB_PHY_REFCLK_CTRL);
|
||
|
|
|
||
|
|
val = readl(CM_DWC_USB2_USB_PHY_HS_PHY_CTRL_COMMON0);
|
||
|
|
val &= ~(7 << 4);
|
||
|
|
val |= (7 << 4);
|
||
|
|
writel(val, CM_DWC_USB2_USB_PHY_HS_PHY_CTRL_COMMON0);
|
||
|
|
}
|
||
|
|
|
||
|
|
void target_usb_phy_reset(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
target_usb_iface_t* target_usb30_init()
|
||
|
|
{
|
||
|
|
target_usb_iface_t *t_usb_iface;
|
||
|
|
|
||
|
|
t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
|
||
|
|
ASSERT(t_usb_iface);
|
||
|
|
|
||
|
|
t_usb_iface->mux_config = target_usb_phy_mux_configure;
|
||
|
|
t_usb_iface->phy_init = target_usb_phy_init;
|
||
|
|
t_usb_iface->phy_reset = target_usb_phy_reset;
|
||
|
|
t_usb_iface->clock_init = clock_usb30_init;
|
||
|
|
t_usb_iface->vbus_override = 1;
|
||
|
|
|
||
|
|
return t_usb_iface;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* identify the usb controller to be used for the target */
|
||
|
|
const char * target_usb_controller()
|
||
|
|
{
|
||
|
|
return "dwc";
|
||
|
|
}
|
||
|
|
|
||
|
|
/* configure hs phy mux if using dwc controller */
|
||
|
|
void target_usb_stop(void)
|
||
|
|
{
|
||
|
|
}
|