253 lines
9.1 KiB
ArmAsm
253 lines
9.1 KiB
ArmAsm
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/*
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* Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Google, Inc. nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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.globl SET_SA
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SET_SA:
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//; routine complete
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B _cpu_early_init_complete
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.ltorg
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.globl __cpu_early_init
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__cpu_early_init:
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//; Zero out r0 for use throughout this code. All other GPRs
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//; (r1-r3) are set throughout this code to help establish
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//; a consistent startup state for any code that follows.
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//; Users should add code at the end of this routine to establish
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//; their own stack address (r13), add translation page tables, enable
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//; the caches, etc.
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MOV r0, #0x0
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//; Remove hardcoded cache settings. appsbl_handler.s calls Set_SA
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//; API to dynamically configure cache for slow/nominal/fast parts
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//; Initialize ASID to zero
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MCR p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0
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//; ICIALL to invalidate entire I-Cache
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MCR p15, 0, r0, c7, c5, 0 //; ICIALLU
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//; Initialize ADFSR to zero
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MCR p15, 0, r0, c5, c1, 0 //; ADFSR r0
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//; Ensure the MCR's above have completed their operation before continuing
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DSB
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ISB
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//;-------------------------------------------------------------------
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//; There are a number of registers that must be set prior to enabling
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//; the MMU. The DCAR is one of these registers. We are setting
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//; it to zero (no access) to easily detect improper setup in subsequent
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//; code sequences
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//;-------------------------------------------------------------------
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//; Setup DACR (Domain Access Control Register) to zero
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MCR p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0
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//;Make sure TLBLKCR is complete before continuing
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ISB
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//; Invalidate the UTLB
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MCR p15, 0, r0, c8, c7, 0 //; UTLBIALL
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//; Make sure UTLB request has been presented to macro before continuing
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ISB
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SYSI2:
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//; Enable Z bit to enable branch prediction (default is off)
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MRC p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2
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ORR r2, r2, #0x00000800
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MCR p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2
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//; Make sure Link stack is initialized with branch and links to sequential addresses
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//; This aids in creating a predictable startup environment
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BL SEQ1
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SEQ1: BL SEQ2
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SEQ2: BL SEQ3
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SEQ3: BL SEQ4
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SEQ4: BL SEQ5
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SEQ5: BL SEQ6
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SEQ6: BL SEQ7
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SEQ7: BL SEQ8
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SEQ8:
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ISB
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//; Initialize the Watchpoint Control Registers to zero (optional)
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//;;; MCR p14, 0, r0, c0, c0, 7 ; WCP14_DBGWCR0 r0
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//;;; MCR p14, 0, r0, c0, c1, 7 ; WCP14_DBGWCR1 r0
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//;----------------------------------------------------------------------
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//; The saved Program Status Registers (SPSRs) should be setup
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//; prior to any automatic mode switches. The following
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//; code sets these registers up to a known state. Users will need to
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//; customize these settings to meet their needs.
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//;----------------------------------------------------------------------
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MOV r2, #0x1f
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MOV r1, #0xd7 //;ABT mode
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msr cpsr_c, r1 //;ABT mode
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msr spsr_cxfs, r2 //;clear the spsr
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MOV r1, #0xdb //;UND mode
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msr cpsr_c, r1 //;UND mode
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msr spsr_cxfs, r2 //;clear the spsr
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MOV r1, #0xd1 //;FIQ mode
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msr cpsr_c, r1 //;FIQ mode
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msr spsr_cxfs, r2 //;clear the spsr
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MOV r1, #0xd2 //;IRQ mode
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msr cpsr_c, r1 //;IRQ mode
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msr spsr_cxfs, r2 //;clear the spsr
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MOV r1, #0xd6 //;Monitor mode
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msr cpsr_c, r1 //;Monitor mode
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msr spsr_cxfs, r2 //;clear the spsr
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MOV r1, #0xd3 //;SVC mode
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msr cpsr_c, r1 //;SVC mode
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msr spsr_cxfs, r2 //;clear the spsr
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//;----------------------------------------------------------------------
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//; Enabling Error reporting is something users may want to do at
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//; some other point in time. We have chosen some default settings
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//; that should be reviewed. Most of these registers come up in an
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//; unpredictable state after reset.
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//;----------------------------------------------------------------------
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//;Start of error and control setting
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//; Set ACTLR (reset unpredictable)
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//; Set AVIVT control, error reporting, etc.
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//; MOV r3, #0x07
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//; Enable I and D cache parity
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//;ACTLR[2:0] = 3'h7 - enable parity error reporting from L2/I$/D$)
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//;ACTLR[5:4] = 2'h3 - enable parity
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//;ACTLR[19:18] =2'h3 - always generate and check parity(when MMU disabled).
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//;Value to be written #0xC0037
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// MOVW r3, #0x0037
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//; .word 0xe3003037 // hardcoded MOVW instruction due to lack of compiler support
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// MOVT r3, #0x000C
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//; .word 0xe340300c // hardcoded MOVW instruction due to lack of compiler support
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//; MCR p15, 0, r3, c1, c0, 1 //; WCP15_ACTLR r3
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//;End of error and control setting
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/*
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#ifdef APPSBL_ETM_ENABLE
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;----------------------------------------------------------------------
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; Optionally Enable the ETM (Embedded Trace Macro) which is used for debug
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;----------------------------------------------------------------------
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; enable ETM clock if disabled
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MRC p15, 7, r1, c15, c0, 5 ; RCP15_CPMR r1
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ORR r1, r1, #0x00000008
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MCR p15, 7, r1, c15, c0, 5 ; WCP15_CPMR r1
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ISB
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; set trigger event to counter1 being zero
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MOV r3, #0x00000040
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MCR p14, 1, r3, c0, c2, 0 ; WCP14_ETMTRIGGER r3
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; clear ETMSR
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MOV r2, #0x00000000
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MCR p14, 1, r2, c0, c4, 0 ; WCP14_ETMSR r2
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; clear trace enable single address comparator usage
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MCR p14, 1, r2, c0, c7, 0 ; WCP14_ETMTECR2 r2
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; set trace enable to always
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MOV r2, #0x0000006F
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MCR p14, 1, r2, c0, c8, 0 ; WCP14_ETMTEEVR r2
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; clear trace enable address range comparator usage and exclude nothing
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MOV r2, #0x01000000
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MCR p14, 1, r2, c0, c9, 0 ; WCP14_ETMTECR1 r2
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; set view data to always
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MOV r2, #0x0000006F
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MCR p14, 1, r2, c0, c12, 0 ; WCP14_ETMVDEVR r2
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; clear view data single address comparator usage
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MOV r2, #0x00000000
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MCR p14, 1, r2, c0, c13, 0 ; WCP14_ETMVDCR1 r2
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; clear view data address range comparator usage and exclude nothing
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MOV r2, #0x00010000
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MCR p14, 1, r2, c0, c15, 0 ; WCP14_ETMVDCR3 r2
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; set counter1 to 194
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MOV r2, #0x000000C2
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MCR p14, 1, r2, c0, c0, 5 ; WCP14_ETMCNTRLDVR1 r2
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; set counter1 to never reload
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MOV r2, #0x0000406F
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MCR p14, 1, r2, c0, c8, 5 ; WCP14_ETMCNTRLDEVR1 r2
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; set counter1 to decrement every cycle
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MOV r2, #0x0000006F
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MCR p14, 1, r2, c0, c4, 5 ; WCP14_ETMCNTENR1 r2
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; Set trace synchronization frequency 1024 bytes
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MOV r2, #0x00000400
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MCR p14, 1, r2, c0, c8, 7 ; WCP14_ETMSYNCFR r2
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; Program etm control register
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; - Set the CPU to ETM clock ratio to 1:1
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; - Set the ETM to perform data address tracing
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MOV r2, #0x00002008
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MCR p14, 1, r2, c0, c0, 0 ; WCP14_ETMCR r2
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ISB
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#endif *//* APPSBL_ETM_ENABLE */
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/*
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#ifdef APPSBL_VFP_ENABLE
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;----------------------------------------------------------------------
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; Perform the following operations if you intend to make use of
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; the VFP/Neon unit. Note that the FMXR instruction requires a CPU ID
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; indicating the VFP unit is present (i.e.Cortex-A8). .
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; Some tools will require full double precision floating point support
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; which will become available in Scorpion pass 2
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;----------------------------------------------------------------------
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; allow full access to CP 10 and 11 space for VFP/NEON use
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MRC p15, 0, r1, c1, c0, 2 ; Read CP Access Control Register
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ORR r1, r1, #0x00F00000 ; enable full access for p10,11
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MCR p15, 0, r1, c1, c0, 2 ; Write CPACR
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;make sure the CPACR is complete before continuing
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ISB
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; Enable VFP itself (certain OSes may want to dynamically set/clear
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; the enable bit based on the application being executed
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MOV r1, #0x40000000
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FMXR FPEXC, r1
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#endif *//* APPSBL_VFP_ENABLE */
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/* we have no stack, so just tail-call into the SET_SA routine... */
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B SET_SA
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.ltorg
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