102 lines
2.2 KiB
ArmAsm
102 lines
2.2 KiB
ArmAsm
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/* init_clock.S -- AT91SAM7 clock coldstart code
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**
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** Copyright 2006, Brian Swetland. All rights reserved.
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** See provided LICENSE file or http://frotz.net/LICENSE for details.
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*/
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.globl init_clock
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init_clock:
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/* init flash controller timing for 18.432MHz */
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mov r1, #0xffffff00
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ldr r0, =0x00340100
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str r0, [r1, #0x60]
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#define PMC_MOR 0x20
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#define PMC_MCFR 0x24
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#define PMC_PLLR 0x2c
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#define PMC_MCKR 0x30
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#define PMC_SR 0x68
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/* PMC_MOR */
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#define PMC_MOSCEN 0x01
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#define PMC_OSCBYPASS 0x02
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/* PMC_MCFR */
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#define PMC_MAINRDY 0x00010000
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/* PMC_SR */
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#define PMC_MOSCS 0x01
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#define PMC_LOCK 0x04
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#define PMC_MCKRDY 0x08
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/* PMC_MCKR */
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#define PMC_CSS_SLOW 0x00
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#define PMC_CSS_MAIN 0x01
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#define PMC_CSS_PLL 0x03
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#define PMC_PRES_NONE 0x00
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#define PMC_PRES_DIV2 0x04
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#define PMC_PRES_DIV4 0x08
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/* Oscillator Init Sequence based on the Atmel sample code
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** in cstartup_boot_SAM7S32_64.s
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**
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** I cleaned it up a bit -- why they use a temporary register,
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** AND and then CMP instead of just TSTing against an immediate
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** boggles my mind. I think this could be a bit simpler yet,
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** but debugging it is a pain, so Good Enough wins for now.
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*/
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ldr r1, =0xfffffc00
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/* bypass main oscillator */
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mov r0, #PMC_OSCBYPASS
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str r0, [r1, #PMC_MOR]
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/* compensate MAINRDY rising flag (45 SCLK) */
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mov r0, #45
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1: subs r0, r0, #1
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bhi 1b
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/* if MAINRDY is set, we have an external oscillator */
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ldr r0, [r1, #PMC_MCFR]
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tst r0, #PMC_MAINRDY
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bne ext_osc_found
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/* reset MOSCS flag */
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mov r0, #0
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str r0, [r1, #PMC_MOR]
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/* enable main oscillator */
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ldr r0, =((0x40 << 8) | PMC_MOSCEN)
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str r0, [r1, #PMC_MOR]
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/* wait for main oscillator to come online */
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1: ldr r0, [r1, #PMC_SR]
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tst r0, #PMC_MOSCS
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beq 1b
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ext_osc_found:
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/* select main oscillator, no prescaler for MCK */
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mov r0, #(PMC_CSS_MAIN | PMC_PRES_NONE)
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str r0, [r1, #PMC_MCKR]
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/* wait until MCK settles to continue */
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1: ldr r0, [r1, #PMC_SR]
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tst r0, #PMC_MCKRDY
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beq 1b
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/* this is a bit of voodoo for selecting a 96.109MHz PLL
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** freq (MUL=72, DIV=14, OUT=0, USBDIV=/1) from the 18.432MHz
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** main clock.
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*/
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ldr r0, =0x10483f0e
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str r0, [r1, #PMC_PLLR]
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/* let the PLL lock before we continue */
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1: ldr r0, [r1, #PMC_SR]
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tst r0, #PMC_LOCK
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beq 1b
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mov pc, lr
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