409 lines
11 KiB
C
409 lines
11 KiB
C
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/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <err.h>
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#include <smem.h>
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#include <msm_panel.h>
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#include <mipi_dsi.h>
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#include "gcdb_autopll.h"
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static struct mdss_dsi_pll_config pll_data;
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static void calculate_bitclock(struct msm_panel_info *pinfo)
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{
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uint32_t h_period = 0, v_period = 0;
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uint32_t width = pinfo->xres;
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struct dsc_desc *dsc = NULL;
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int bpp_lane;
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if (pinfo->mipi.dual_dsi)
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width /= 2;
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if (pinfo->compression_mode == COMPRESSION_DSC) {
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dsc = &pinfo->dsc;
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width = dsc->pclk_per_line;
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} else if (pinfo->compression_mode == COMPRESSION_FBC) {
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if (pinfo->fbc.comp_ratio)
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width /= pinfo->fbc.comp_ratio;
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}
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h_period = width + pinfo->lcdc.h_back_porch +
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pinfo->lcdc.h_front_porch + pinfo->lcdc.h_pulse_width +
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pinfo->lcdc.xres_pad;
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v_period = pinfo->yres + pinfo->lcdc.v_back_porch +
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pinfo->lcdc.v_front_porch + pinfo->lcdc.v_pulse_width +
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pinfo->lcdc.yres_pad;
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bpp_lane = pinfo->bpp / pinfo->mipi.num_of_lanes;
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/*
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* If a bit clock rate is not specified, calculate it based
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* on panel parameters
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*/
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if (pinfo->mipi.bitclock == 0)
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pll_data.bit_clock = (h_period * v_period *
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pinfo->mipi.frame_rate * bpp_lane);
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else
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pll_data.bit_clock = pinfo->mipi.bitclock;
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pll_data.pixel_clock = (pll_data.bit_clock / bpp_lane);
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dprintf(SPEW, "%s: bit_clk=%d pix_clk=%d\n", __func__,
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pll_data.bit_clock, pll_data.pixel_clock);
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pll_data.byte_clock = pll_data.bit_clock >> 3;
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pll_data.halfbit_clock = pll_data.bit_clock >> 1;
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}
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static uint32_t calculate_div1()
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{
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uint32_t ret = NO_ERROR;
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/* div1 - there is divide by 2 logic present */
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if (pll_data.halfbit_clock > HALFBIT_CLOCK1) {
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pll_data.posdiv1 = 0x0; /*div 1 */
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pll_data.vco_clock = pll_data.halfbit_clock << 1;
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} else if (pll_data.halfbit_clock > HALFBIT_CLOCK2) {
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pll_data.posdiv1 = 0x1; /*div 2 */
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pll_data.vco_clock = pll_data.halfbit_clock << 2;
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} else if (pll_data.halfbit_clock > HALFBIT_CLOCK3) {
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pll_data.posdiv1 = 0x3; /*div 4 */
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pll_data.vco_clock = pll_data.halfbit_clock << 3;
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} else if (pll_data.halfbit_clock > HALFBIT_CLOCK4) {
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pll_data.posdiv1 = 0x4; /*div 5 */
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pll_data.vco_clock = pll_data.halfbit_clock * 10;
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} else {
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dprintf(CRITICAL, "Not able to calculate posdiv1\n");
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}
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return ret;
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}
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static uint32_t calculate_div3(uint8_t bpp, uint8_t num_of_lanes)
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{
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pll_data.pclk_m = 0x1; /* M = 1, N= 1 */
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pll_data.pclk_n = 0xFF; /* ~ (N-M) = 0xff */
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pll_data.pclk_d = 0xFF; /* ~N = 0xFF */
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/* formula is ( vco_clock / pdiv_digital) / mnd = pixel_clock */
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/* div3 */
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switch (bpp) {
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case BITS_18:
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if (num_of_lanes == 3) {
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pll_data.posdiv3 = pll_data.vco_clock /
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pll_data.pixel_clock;
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} else {
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pll_data.posdiv3 = (pll_data.pixel_clock * 2 / 9) /
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pll_data.vco_clock;
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pll_data.pclk_m = 0x2; /* M = 2,N = 9 */
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pll_data.pclk_n = 0xF8;
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pll_data.pclk_d = 0xF6;
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}
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break;
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case BITS_16:
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if (num_of_lanes == 3) {
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pll_data.posdiv3 = (pll_data.pixel_clock * 3 / 8) /
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pll_data.vco_clock;
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pll_data.pclk_m = 0x3; /* M = 3, N = 9 */
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pll_data.pclk_n = 0xFA;
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pll_data.pclk_d = 0xF7;
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} else {
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pll_data.posdiv3 = pll_data.vco_clock /
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pll_data.pixel_clock;
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}
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break;
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case BITS_24:
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default:
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pll_data.posdiv3 = pll_data.vco_clock /
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pll_data.pixel_clock;
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break;
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}
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pll_data.posdiv3--; /* Register needs one value less */
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return NO_ERROR;
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}
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static uint32_t calculate_dec_frac_start()
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{
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uint32_t refclk = 19200000;
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uint32_t vco_rate = pll_data.vco_clock;
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uint32_t tmp, mod;
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vco_rate /= 2;
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pll_data.dec_start = vco_rate / refclk;
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tmp = vco_rate % refclk; /* module, fraction */
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tmp /= 192;
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tmp *= 1024;
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tmp /= 100;
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tmp *= 1024;
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tmp /= 1000;
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pll_data.frac_start = tmp;
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vco_rate *= 2; /* restore */
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if (pll_data.en_vco_zero_phase) {
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tmp = vco_rate / (refclk / 1000);/* div 1000 first */
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tmp *= 1024;
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tmp /= 1000;
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tmp /= 10;
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pll_data.lock_comp = tmp - 1;
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} else {
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tmp = vco_rate / refclk;
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mod = vco_rate % refclk;
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tmp *= 127;
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mod *= 127;
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mod /= refclk;
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tmp += mod;
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tmp /= 10;
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pll_data.lock_comp = tmp;
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}
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dprintf(SPEW, "%s: dec_start=0x%x dec_frac=0x%x lock_comp=0x%x\n", __func__,
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pll_data.dec_start, pll_data.frac_start, pll_data.lock_comp);
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return NO_ERROR;
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}
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static uint32_t calculate_vco_28nm(uint8_t bpp, uint8_t num_of_lanes)
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{
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/* If half bitclock is more than VCO min value */
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if (pll_data.halfbit_clock > VCO_MIN_CLOCK) {
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/* Direct Mode */
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/* support vco clock to max value only */
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if (pll_data.halfbit_clock > VCO_MAX_CLOCK)
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pll_data.vco_clock = VCO_MAX_CLOCK;
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else
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pll_data.vco_clock = pll_data.halfbit_clock;
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pll_data.directpath = 0x0;
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pll_data.posdiv1 = 0x0; /*DSI spec says 0 - div 1 */
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/*1 - div 2 */
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/*F - div 16 */
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} else {
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/* Indirect Mode */
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pll_data.directpath = 0x02; /* set bit 1 to enable for
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indirect path */
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calculate_div1();
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}
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/* calculate mnd and div3 for direct and indirect path */
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calculate_div3(bpp, num_of_lanes);
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return NO_ERROR;
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}
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#ifndef DISPLAY_EN_20NM_PLL_90_PHASE
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static void config_20nm_pll_vco_range(void)
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{
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pll_data.vco_min = 300000000;
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pll_data.vco_max = 1500000000;
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pll_data.en_vco_zero_phase = 1;
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dprintf(SPEW, "%s: Configured VCO for zero phase\n", __func__);
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}
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#else
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static void config_20nm_pll_vco_range(void)
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{
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pll_data.vco_min = 1000000000;
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pll_data.vco_max = 2000000000;
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pll_data.en_vco_zero_phase = 0;
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dprintf(SPEW, "%s: Configured VCO for 90 phase\n", __func__);
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}
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#endif
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static uint32_t calculate_vco_thulium()
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{
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uint32_t rate;
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uint32_t mod;
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pll_data.vco_min = MIN_THULIUM_VCO_RATE;
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pll_data.vco_max = MAX_THULIUM_VCO_RATE;
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if (pll_data.bit_clock < pll_data.vco_min)
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rate = pll_data.vco_min;
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else if (pll_data.bit_clock > pll_data.vco_max)
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rate = pll_data.vco_max;
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else
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rate = pll_data.bit_clock;
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pll_data.ndiv = FIX_N_DIV;
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if (pll_data.bit_clock) {
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pll_data.n1div = rate / pll_data.bit_clock;
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} else {
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dprintf(ERROR, "%s: bit clock is 0, divider calculation failed\n",
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__func__);
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return ERROR;
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}
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mod = rate % pll_data.bit_clock;
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if (mod)
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pll_data.n1div++;
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if (pll_data.n1div < MIN_THULIUM_DIV_VAL ||
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pll_data.n1div > MAX_THULIUM_DIV_VAL) {
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dprintf(ERROR, "%s: n1div is out of ranget:%d\n",
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__func__, pll_data.n1div);
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return ERROR;
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}
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pll_data.vco_clock = pll_data.bit_clock * pll_data.ndiv *
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pll_data.n1div;
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rate = pll_data.vco_clock;
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rate /= pll_data.n1div;
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rate /= FIX_PIXEL_CLOCK_DIV;
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pll_data.n2div = rate / pll_data.pixel_clock;
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mod = rate % pll_data.pixel_clock;
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if (mod)
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pll_data.n2div++;
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if (pll_data.n2div < MIN_THULIUM_DIV_VAL ||
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pll_data.n2div > MAX_THULIUM_DIV_VAL) {
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dprintf(ERROR, "%s: n2div is out of ranget:%d\n",
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__func__, pll_data.n2div);
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return ERROR;
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}
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dprintf(SPEW, "%s: vco:%u n1div:%d n2div:%d bit_clk:%u pixel_clk:%u\n",
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__func__, pll_data.vco_clock, pll_data.n1div, pll_data.n2div,
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pll_data.bit_clock, pll_data.pixel_clock);
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return NO_ERROR;
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}
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static uint32_t calculate_vco_20nm(uint8_t bpp, uint8_t lanes)
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{
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uint32_t vco, dsi_clk;
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int mod, ndiv, hr_oclk2, hr_oclk3;
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int m = 1;
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int n = 1;
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int bpp_m = 3; /* bpp = 3 */
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int bpp_n = 1;
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if (bpp == BITS_18) {
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bpp_m = 9; /* bpp = 2.25 */
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bpp_n = 4;
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if (lanes == 2) {
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m = 2;
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n = 9;
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} else if (lanes == 4) {
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m = 4;
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n = 9;
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}
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} else if (bpp == BITS_16) {
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bpp_m = 2; /* bpp = 2 */
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bpp_n = 1;
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if (lanes == 3) {
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m = 3;
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n = 8;
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}
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}
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hr_oclk2 = 4;
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/* If bitclock is more than VCO min value */
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if (pll_data.halfbit_clock >= ((pll_data.vco_min) >> 1)) {
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/* Direct Mode */
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vco = pll_data.halfbit_clock << 1;
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/* support vco clock to max value only */
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if (vco > (pll_data.vco_max))
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vco = (pll_data.vco_max);
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pll_data.directpath = 0x0;
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pll_data.byte_clock = vco / 2 / hr_oclk2;
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pll_data.lp_div_mux = 0x0;
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ndiv = 1;
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hr_oclk3 = hr_oclk2 * m / n * bpp_m / bpp_n / lanes;
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} else {
|
||
|
|
/* Indirect Mode */
|
||
|
|
mod = (pll_data.vco_min) % (4 * pll_data.halfbit_clock );
|
||
|
|
ndiv = (pll_data.vco_min) / (4 * pll_data.halfbit_clock );
|
||
|
|
if (mod)
|
||
|
|
ndiv += 1;
|
||
|
|
|
||
|
|
vco = pll_data.halfbit_clock * 4 * ndiv;
|
||
|
|
pll_data.lp_div_mux = 0x1;
|
||
|
|
pll_data.directpath = 0x02; /* set bit 1 to enable for
|
||
|
|
indirect path */
|
||
|
|
|
||
|
|
pll_data.byte_clock = vco / 4 / hr_oclk2 / ndiv;
|
||
|
|
hr_oclk3 = hr_oclk2 * m / n * ndiv * 2 * bpp_m / bpp_n / lanes;
|
||
|
|
}
|
||
|
|
|
||
|
|
pll_data.vco_clock = vco;
|
||
|
|
dsi_clk = vco / 2 / hr_oclk3;
|
||
|
|
pll_data.ndiv = ndiv;
|
||
|
|
pll_data.hr_oclk2 = hr_oclk2 - 1; /* strat from 0 */
|
||
|
|
pll_data.hr_oclk3 = hr_oclk3 - 1; /* strat from 0 */
|
||
|
|
|
||
|
|
pll_data.pclk_m = m; /* M */
|
||
|
|
pll_data.pclk_n = ~(n - m); /* ~(N-M) */
|
||
|
|
pll_data.pclk_d = ~n; /* ~N */
|
||
|
|
|
||
|
|
dprintf(SPEW, "%s: oclk2=%d oclk3=%d ndiv=%d vco=%u dsi_clk=%u byte_clk=%u\n",
|
||
|
|
__func__, hr_oclk2, hr_oclk3, ndiv, vco, dsi_clk, pll_data.byte_clock);
|
||
|
|
|
||
|
|
calculate_dec_frac_start();
|
||
|
|
|
||
|
|
return NO_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t calculate_clock_config(struct msm_panel_info *pinfo)
|
||
|
|
{
|
||
|
|
uint32_t ret = NO_ERROR;
|
||
|
|
|
||
|
|
calculate_bitclock(pinfo);
|
||
|
|
|
||
|
|
switch (pinfo->mipi.mdss_dsi_phy_db->pll_type) {
|
||
|
|
case DSI_PLL_TYPE_20NM:
|
||
|
|
config_20nm_pll_vco_range();
|
||
|
|
ret = calculate_vco_20nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
|
||
|
|
break;
|
||
|
|
case DSI_PLL_TYPE_THULIUM:
|
||
|
|
ret = calculate_vco_thulium(pinfo->bpp, pinfo->mipi.num_of_lanes);
|
||
|
|
break;
|
||
|
|
case DSI_PLL_TYPE_28NM:
|
||
|
|
default:
|
||
|
|
ret = calculate_vco_28nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
pinfo->mipi.dsi_pll_config = &pll_data;
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|