199 lines
5.8 KiB
C
199 lines
5.8 KiB
C
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/*
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* Copyright (C) 2008 The Android Open Source Project
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_MACHINE_CPU_FEATURES_H
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#define _ARM_MACHINE_CPU_FEATURES_H
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/* The purpose of this file is to define several macros corresponding
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* to CPU features that may or may not be available at build time on
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* on the target CPU.
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*
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* This is done to abstract us from the various ARM Architecture
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* quirks and alphabet soup.
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*
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* IMPORTANT: We have no intention to support anything below an ARMv4T !
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*/
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/* __ARM_ARCH__ is a number corresponding to the ARM revision
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* we're going to support
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*
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* it looks like our toolchain doesn't define __ARM_ARCH__
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* so try to guess it.
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*
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*
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*
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*/
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#ifndef __ARM_ARCH__
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# if defined __ARM_ARCH_7__ || defined __ARM_ARCH_7A__ || \
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defined __ARM_ARCH_7R__ || defined __ARM_ARCH_7M__
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# define __ARM_ARCH__ 7
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# elif defined __ARM_ARCH_6__ || defined __ARM_ARCH_6J__ || \
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defined __ARM_ARCH_6K__ || defined __ARM_ARCH_6Z__ || \
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defined __ARM_ARCH_6KZ__ || defined __ARM_ARCH_6T2__
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#
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# define __ARM_ARCH__ 6
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#
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# elif defined __ARM_ARCH_5__ || defined __ARM_ARCH_5T__ || \
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defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__
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#
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# define __ARM_ARCH__ 5
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#
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# elif defined __ARM_ARCH_4T__
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#
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# define __ARM_ARCH__ 4
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#
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# elif defined __ARM_ARCH_4__
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# error ARMv4 is not supported, please use ARMv4T at a minimum
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# else
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# error Unknown or unsupported ARM architecture
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# endif
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#endif
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/* experimental feature used to check that our ARMv4 workarounds
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* work correctly without a real ARMv4 machine */
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#ifdef BIONIC_EXPERIMENTAL_FORCE_ARMV4
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# undef __ARM_ARCH__
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# define __ARM_ARCH__ 4
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#endif
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/* define __ARM_HAVE_5TE if we have the ARMv5TE instructions */
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#if __ARM_ARCH__ > 5
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# define __ARM_HAVE_5TE 1
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#elif __ARM_ARCH__ == 5
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# if defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__
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# define __ARM_HAVE_5TE 1
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# endif
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#endif
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/* instructions introduced in ARMv5 */
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#if __ARM_ARCH__ >= 5
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# define __ARM_HAVE_BLX 1
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# define __ARM_HAVE_CLZ 1
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# define __ARM_HAVE_LDC2 1
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# define __ARM_HAVE_MCR2 1
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# define __ARM_HAVE_MRC2 1
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# define __ARM_HAVE_STC2 1
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#endif
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/* ARMv5TE introduces a few instructions */
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#if __ARM_HAVE_5TE
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# define __ARM_HAVE_PLD 1
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# define __ARM_HAVE_MCRR 1
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# define __ARM_HAVE_MRRC 1
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#endif
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/* define __ARM_HAVE_HALFWORD_MULTIPLY when half-word multiply instructions
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* this means variants of: smul, smulw, smla, smlaw, smlal
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*/
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#if __ARM_HAVE_5TE
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# define __ARM_HAVE_HALFWORD_MULTIPLY 1
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#endif
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/* define __ARM_HAVE_PAIR_LOAD_STORE when 64-bit memory loads and stored
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* into/from a pair of 32-bit registers is supported throuhg 'ldrd' and 'strd'
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*/
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#if __ARM_HAVE_5TE
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# define __ARM_HAVE_PAIR_LOAD_STORE 1
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#endif
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/* define __ARM_HAVE_SATURATED_ARITHMETIC is you have the saturated integer
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* arithmetic instructions: qdd, qdadd, qsub, qdsub
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*/
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#if __ARM_HAVE_5TE
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# define __ARM_HAVE_SATURATED_ARITHMETIC 1
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#endif
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/* define __ARM_HAVE_PC_INTERWORK when a direct assignment to the
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* pc register will switch into thumb/ARM mode depending on bit 0
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* of the new instruction address. Before ARMv5, this was not the
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* case, and you have to write:
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*
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* mov r0, [<some address>]
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* bx r0
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*
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* instead of:
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*
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* ldr pc, [<some address>]
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*
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* note that this affects any instruction that explicitly changes the
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* value of the pc register, including ldm { ...,pc } or 'add pc, #offset'
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*/
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#if __ARM_ARCH__ >= 5
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# define __ARM_HAVE_PC_INTERWORK
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#endif
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/* define __ARM_HAVE_LDREX_STREX for ARMv6 and ARMv7 architecture to be
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* used in replacement of deprecated swp instruction
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*/
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#if __ARM_ARCH__ >= 6
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# define __ARM_HAVE_LDREX_STREX
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#endif
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/* define __ARM_HAVE_DMB for ARMv7 architecture
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*/
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#if __ARM_ARCH__ >= 7
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# define __ARM_HAVE_DMB
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#endif
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/* define __ARM_HAVE_LDREXD for ARMv7 architecture
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* (also present in ARMv6K, but not implemented in ARMv7-M, neither of which
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* we care about)
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*/
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#if __ARM_ARCH__ >= 7
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# define __ARM_HAVE_LDREXD
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#endif
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/* define _ARM_HAVE_VFP if we have VFPv3
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*/
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#if __ARM_ARCH__ >= 7 && defined __VFP_FP__
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# define __ARM_HAVE_VFP
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#endif
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/* define _ARM_HAVE_NEON for ARMv7 architecture if we support the
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* Neon SIMD instruction set extensions. This also implies
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* that VFPv3-D32 is supported.
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*/
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#if __ARM_ARCH__ >= 7 && defined __ARM_NEON__
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# define __ARM_HAVE_NEON
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#endif
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/* Assembly-only macros */
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/* define a handy PLD(address) macro since the cache preload
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* is an optional opcode
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*/
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#if __ARM_HAVE_PLD
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# define PLD(reg,offset) pld [reg, offset]
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#else
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# define PLD(reg,offset) /* nothing */
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#endif
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#endif /* _ARM_MACHINE_CPU_FEATURES_H */
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