596 lines
15 KiB
C
596 lines
15 KiB
C
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#ifndef __LINUX_TAVARUA_H
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#define __LINUX_TAVARUA_H
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <asm/sizes.h>
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#else
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#include <stdint.h>
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#endif
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#include <linux/ioctl.h>
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#include <linux/videodev2.h>
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#undef FM_DEBUG
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/* constants */
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#define RDS_BLOCKS_NUM (4)
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#define BYTES_PER_BLOCK (3)
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#define MAX_PS_LENGTH (96)
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#define MAX_RT_LENGTH (64)
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#define RX_STATIONS0_LEN (15)
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#define XFRDAT0 (0x20)
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#define XFRDAT1 (0x21)
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#define XFRDAT2 (0x22)
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#define INTDET_PEEK_MSB (0x88)
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#define INTDET_PEEK_LSB (0x26)
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#define RMSSI_PEEK_MSB (0x88)
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#define RMSSI_PEEK_LSB (0xA8)
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#define MPX_DCC_BYPASS_POKE_MSB (0x88)
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#define MPX_DCC_BYPASS_POKE_LSB (0xC0)
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#define MPX_DCC_PEEK_MSB_REG1 (0x88)
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#define MPX_DCC_PEEK_LSB_REG1 (0xC2)
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#define MPX_DCC_PEEK_MSB_REG2 (0x88)
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#define MPX_DCC_PEEK_LSB_REG2 (0xC3)
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#define MPX_DCC_PEEK_MSB_REG3 (0x88)
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#define MPX_DCC_PEEK_LSB_REG3 (0xC4)
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#define ON_CHANNEL_TH_MSB (0x0B)
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#define ON_CHANNEL_TH_LSB (0xA8)
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#define OFF_CHANNEL_TH_MSB (0x0B)
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#define OFF_CHANNEL_TH_LSB (0xAC)
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#define ENF_200Khz (1)
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#define SRCH200KHZ_OFFSET (7)
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#define SRCH_MASK (1 << SRCH200KHZ_OFFSET)
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/* Standard buffer size */
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#define STD_BUF_SIZE (256)
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/* Search direction */
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#define SRCH_DIR_UP (0)
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#define SRCH_DIR_DOWN (1)
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/* control options */
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#define CTRL_ON (1)
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#define CTRL_OFF (0)
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#define US_LOW_BAND (87.5)
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#define US_HIGH_BAND (108)
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/* constant for Tx */
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#define MASK_PI (0x0000FFFF)
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#define MASK_PI_MSB (0x0000FF00)
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#define MASK_PI_LSB (0x000000FF)
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#define MASK_PTY (0x0000001F)
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#define MASK_TXREPCOUNT (0x0000000F)
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#undef FMDBG
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#ifdef FM_DEBUG
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#define FMDBG(fmt, args...) printk(KERN_INFO "tavarua_radio: " fmt, ##args)
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#else
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#define FMDBG(fmt, args...)
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#endif
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#undef FMDERR
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#define FMDERR(fmt, args...) printk(KERN_INFO "tavarua_radio: " fmt, ##args)
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#undef FMDBG_I2C
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#ifdef FM_DEBUG_I2C
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#define FMDBG_I2C(fmt, args...) printk(KERN_INFO "fm_i2c: " fmt, ##args)
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#else
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#define FMDBG_I2C(fmt, args...)
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#endif
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/* function declarations */
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/* FM Core audio paths. */
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#define TAVARUA_AUDIO_OUT_ANALOG_OFF (0)
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#define TAVARUA_AUDIO_OUT_ANALOG_ON (1)
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#define TAVARUA_AUDIO_OUT_DIGITAL_OFF (0)
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#define TAVARUA_AUDIO_OUT_DIGITAL_ON (1)
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int tavarua_set_audio_path(int digital_on, int analog_on);
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/* defines and enums*/
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#define MARIMBA_A0 0x01010013
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#define MARIMBA_2_1 0x02010204
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#define BAHAMA_1_0 0x0302010A
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#define BAHAMA_2_0 0x04020205
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#define BAHAMA_2_1 0x04020309
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#define WAIT_TIMEOUT 2000
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#define RADIO_INIT_TIME 15
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#define TAVARUA_DELAY 10
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/*
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* The frequency is set in units of 62.5 Hz when using V4L2_TUNER_CAP_LOW,
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* 62.5 kHz otherwise.
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* The tuner is able to have a channel spacing of 50, 100 or 200 kHz.
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* tuner->capability is therefore set to V4L2_TUNER_CAP_LOW
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* The FREQ_MUL is then: 1 MHz / 62.5 Hz = 16000
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*/
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#define FREQ_MUL (1000000 / 62.5)
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enum v4l2_cid_private_tavarua_t {
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V4L2_CID_PRIVATE_TAVARUA_SRCHMODE = (V4L2_CID_PRIVATE_BASE + 1),
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V4L2_CID_PRIVATE_TAVARUA_SCANDWELL,
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V4L2_CID_PRIVATE_TAVARUA_SRCHON,
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V4L2_CID_PRIVATE_TAVARUA_STATE,
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V4L2_CID_PRIVATE_TAVARUA_TRANSMIT_MODE,
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V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_MASK,
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V4L2_CID_PRIVATE_TAVARUA_REGION,
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V4L2_CID_PRIVATE_TAVARUA_SIGNAL_TH,
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V4L2_CID_PRIVATE_TAVARUA_SRCH_PTY,
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V4L2_CID_PRIVATE_TAVARUA_SRCH_PI,
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V4L2_CID_PRIVATE_TAVARUA_SRCH_CNT,
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V4L2_CID_PRIVATE_TAVARUA_EMPHASIS,
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V4L2_CID_PRIVATE_TAVARUA_RDS_STD,
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V4L2_CID_PRIVATE_TAVARUA_SPACING,
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V4L2_CID_PRIVATE_TAVARUA_RDSON,
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V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_PROC,
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V4L2_CID_PRIVATE_TAVARUA_LP_MODE,
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V4L2_CID_PRIVATE_TAVARUA_ANTENNA,
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V4L2_CID_PRIVATE_TAVARUA_RDSD_BUF,
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V4L2_CID_PRIVATE_TAVARUA_PSALL,
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/*v4l2 Tx controls*/
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V4L2_CID_PRIVATE_TAVARUA_TX_SETPSREPEATCOUNT,
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V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_PS_NAME,
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V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_RT,
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V4L2_CID_PRIVATE_TAVARUA_IOVERC,
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V4L2_CID_PRIVATE_TAVARUA_INTDET,
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V4L2_CID_PRIVATE_TAVARUA_MPX_DCC,
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V4L2_CID_PRIVATE_TAVARUA_AF_JUMP,
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V4L2_CID_PRIVATE_TAVARUA_RSSI_DELTA,
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V4L2_CID_PRIVATE_TAVARUA_HLSI,
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/*
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* Here we have IOCTl's that are specific to IRIS
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* (V4L2_CID_PRIVATE_BASE + 0x1E to V4L2_CID_PRIVATE_BASE + 0x28)
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*/
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V4L2_CID_PRIVATE_SOFT_MUTE,/* 0x800001E*/
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V4L2_CID_PRIVATE_RIVA_ACCS_ADDR,
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V4L2_CID_PRIVATE_RIVA_ACCS_LEN,
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V4L2_CID_PRIVATE_RIVA_PEEK,
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V4L2_CID_PRIVATE_RIVA_POKE,
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V4L2_CID_PRIVATE_SSBI_ACCS_ADDR,
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V4L2_CID_PRIVATE_SSBI_PEEK,
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V4L2_CID_PRIVATE_SSBI_POKE,
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V4L2_CID_PRIVATE_TX_TONE,
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V4L2_CID_PRIVATE_RDS_GRP_COUNTERS,
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V4L2_CID_PRIVATE_SET_NOTCH_FILTER,/* 0x8000028 */
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V4L2_CID_PRIVATE_TAVARUA_SET_AUDIO_PATH,/* 0x8000029 */
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V4L2_CID_PRIVATE_TAVARUA_DO_CALIBRATION,/* 0x800002A : IRIS */
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V4L2_CID_PRIVATE_TAVARUA_SRCH_ALGORITHM,/* 0x800002B */
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V4L2_CID_PRIVATE_IRIS_GET_SINR, /* 0x800002C : IRIS */
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V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD, /* 0x800002D */
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V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD, /* 0x800002E */
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V4L2_CID_PRIVATE_SINR_THRESHOLD, /* 0x800002F : IRIS */
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V4L2_CID_PRIVATE_SINR_SAMPLES, /* 0x8000030 : IRIS */
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V4L2_CID_PRIVATE_SPUR_FREQ,
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V4L2_CID_PRIVATE_SPUR_FREQ_RMSSI,
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V4L2_CID_PRIVATE_SPUR_SELECTION,
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V4L2_CID_PRIVATE_UPDATE_SPUR_TABLE,
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V4L2_CID_PRIVATE_VALID_CHANNEL,
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};
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enum tavarua_buf_t {
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TAVARUA_BUF_SRCH_LIST,
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TAVARUA_BUF_EVENTS,
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TAVARUA_BUF_RT_RDS,
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TAVARUA_BUF_PS_RDS,
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TAVARUA_BUF_RAW_RDS,
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TAVARUA_BUF_AF_LIST,
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TAVARUA_BUF_MAX
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};
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enum tavarua_xfr_t {
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TAVARUA_XFR_SYNC,
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TAVARUA_XFR_ERROR,
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TAVARUA_XFR_SRCH_LIST,
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TAVARUA_XFR_RT_RDS,
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TAVARUA_XFR_PS_RDS,
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TAVARUA_XFR_AF_LIST,
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TAVARUA_XFR_MAX
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};
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enum channel_spacing {
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FM_CH_SPACE_200KHZ,
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FM_CH_SPACE_100KHZ,
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FM_CH_SPACE_50KHZ
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};
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enum step_size {
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NO_SRCH200khz,
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ENF_SRCH200khz
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};
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enum emphasis {
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EMP_75,
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EMP_50
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};
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enum rds_std {
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RBDS_STD,
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RDS_STD
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};
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/* offsets */
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#define RAW_RDS 0x0F
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#define RDS_BLOCK 3
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/* registers*/
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#define MARIMBA_XO_BUFF_CNTRL 0x07
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#define RADIO_REGISTERS 0x30
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#define XFR_REG_NUM 16
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#define STATUS_REG_NUM 3
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/* TX constants */
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#define HEADER_SIZE 4
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#define TX_ON 0x80
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#define TAVARUA_TX_RT RDS_RT_0
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#define TAVARUA_TX_PS RDS_PS_0
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enum register_t {
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STATUS_REG1 = 0,
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STATUS_REG2,
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STATUS_REG3,
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RDCTRL,
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FREQ,
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TUNECTRL,
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SRCHRDS1,
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SRCHRDS2,
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SRCHCTRL,
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IOCTRL,
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RDSCTRL,
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ADVCTRL,
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AUDIOCTRL,
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RMSSI,
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IOVERC,
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AUDIOIND = 0x1E,
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XFRCTRL,
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FM_CTL0 = 0xFF,
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LEAKAGE_CNTRL = 0xFE,
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};
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#define BAHAMA_RBIAS_CTL1 0x07
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#define BAHAMA_FM_MODE_REG 0xFD
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#define BAHAMA_FM_CTL1_REG 0xFE
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#define BAHAMA_FM_CTL0_REG 0xFF
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#define BAHAMA_FM_MODE_NORMAL 0x00
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#define BAHAMA_LDO_DREG_CTL0 0xF0
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#define BAHAMA_LDO_AREG_CTL0 0xF4
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/* Radio Control */
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#define RDCTRL_STATE_OFFSET 0
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#define RDCTRL_STATE_MASK (3 << RDCTRL_STATE_OFFSET)
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#define RDCTRL_BAND_OFFSET 2
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#define RDCTRL_BAND_MASK (1 << RDCTRL_BAND_OFFSET)
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#define RDCTRL_CHSPACE_OFFSET 3
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#define RDCTRL_CHSPACE_MASK (3 << RDCTRL_CHSPACE_OFFSET)
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#define RDCTRL_DEEMPHASIS_OFFSET 5
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#define RDCTRL_DEEMPHASIS_MASK (1 << RDCTRL_DEEMPHASIS_OFFSET)
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#define RDCTRL_HLSI_OFFSET 6
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#define RDCTRL_HLSI_MASK (3 << RDCTRL_HLSI_OFFSET)
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#define RDSAF_OFFSET 6
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#define RDSAF_MASK (1 << RDSAF_OFFSET)
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/* Tune Control */
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#define TUNE_STATION 0x01
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#define ADD_OFFSET (1 << 1)
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#define SIGSTATE (1 << 5)
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#define MOSTSTATE (1 << 6)
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#define RDSSYNC (1 << 7)
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/* Search Control */
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#define SRCH_MODE_OFFSET 0
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#define SRCH_MODE_MASK (7 << SRCH_MODE_OFFSET)
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#define SRCH_DIR_OFFSET 3
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#define SRCH_DIR_MASK (1 << SRCH_DIR_OFFSET)
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#define SRCH_DWELL_OFFSET 4
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#define SRCH_DWELL_MASK (7 << SRCH_DWELL_OFFSET)
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#define SRCH_STATE_OFFSET 7
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#define SRCH_STATE_MASK (1 << SRCH_STATE_OFFSET)
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/* I/O Control */
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#define IOC_HRD_MUTE 0x03
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#define IOC_SFT_MUTE (1 << 2)
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#define IOC_MON_STR (1 << 3)
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#define IOC_SIG_BLND (1 << 4)
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#define IOC_INTF_BLND (1 << 5)
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#define IOC_ANTENNA (1 << 6)
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#define IOC_ANTENNA_OFFSET 6
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#define IOC_ANTENNA_MASK (1 << IOC_ANTENNA_OFFSET)
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/* RDS Control */
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#define RDS_ON 0x01
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#define RDSCTRL_STANDARD_OFFSET 1
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#define RDSCTRL_STANDARD_MASK (1 << RDSCTRL_STANDARD_OFFSET)
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/* Advanced features controls */
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#define RDSRTEN (1 << 3)
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#define RDSPSEN (1 << 4)
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/* Audio path control */
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#define AUDIORX_ANALOG_OFFSET 0
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#define AUDIORX_ANALOG_MASK (1 << AUDIORX_ANALOG_OFFSET)
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#define AUDIORX_DIGITAL_OFFSET 1
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#define AUDIORX_DIGITAL_MASK (1 << AUDIORX_DIGITAL_OFFSET)
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#define AUDIOTX_OFFSET 2
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#define AUDIOTX_MASK (1 << AUDIOTX_OFFSET)
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||
|
|
#define I2SCTRL_OFFSET 3
|
||
|
|
#define I2SCTRL_MASK (1 << I2SCTRL_OFFSET)
|
||
|
|
|
||
|
|
/* Search options */
|
||
|
|
enum search_t {
|
||
|
|
SEEK,
|
||
|
|
SCAN,
|
||
|
|
SCAN_FOR_STRONG,
|
||
|
|
SCAN_FOR_WEAK,
|
||
|
|
RDS_SEEK_PTY,
|
||
|
|
RDS_SCAN_PTY,
|
||
|
|
RDS_SEEK_PI,
|
||
|
|
RDS_AF_JUMP,
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Band limits */
|
||
|
|
#define REGION_US_EU_BAND_LOW 87500
|
||
|
|
#define REGION_US_EU_BAND_HIGH 108000
|
||
|
|
#define REGION_JAPAN_STANDARD_BAND_LOW 76000
|
||
|
|
#define REGION_JAPAN_STANDARD_BAND_HIGH 90000
|
||
|
|
#define REGION_JAPAN_WIDE_BAND_LOW 90000
|
||
|
|
#define REGION_JAPAN_WIDE_BAND_HIGH 108000
|
||
|
|
#define MPX_DCC_BYPASS_REG 0x88C0
|
||
|
|
#define MPX_DCC_DATA_REG 0x88C2
|
||
|
|
|
||
|
|
enum audio_path {
|
||
|
|
FM_DIGITAL_PATH,
|
||
|
|
FM_ANALOG_PATH
|
||
|
|
};
|
||
|
|
#define SRCH_MODE 0x07
|
||
|
|
#define SRCH_DIR 0x08 /* 0-up 1-down */
|
||
|
|
#define SCAN_DWELL 0x70
|
||
|
|
#define SRCH_ON 0x80
|
||
|
|
|
||
|
|
/* RDS CONFIG */
|
||
|
|
#define RDS_CONFIG_PSALL 0x01
|
||
|
|
|
||
|
|
#define FM_ENABLE 0x22
|
||
|
|
#define SET_REG_FIELD(reg, val, offset, mask) \
|
||
|
|
(reg = (reg & ~mask) | (((val) << offset) & mask))
|
||
|
|
#define GET_REG_FIELD(reg, offset, mask) ((reg & mask) >> offset)
|
||
|
|
#define RSH_DATA(val, offset) ((val) >> (offset))
|
||
|
|
#define LSH_DATA(val, offset) ((val) << (offset))
|
||
|
|
#define GET_ABS_VAL(val) ((val) & (0xFF))
|
||
|
|
|
||
|
|
enum radio_state_t {
|
||
|
|
FM_OFF,
|
||
|
|
FM_RECV,
|
||
|
|
FM_TRANS,
|
||
|
|
FM_RESET,
|
||
|
|
};
|
||
|
|
|
||
|
|
#define XFRCTRL_WRITE (1 << 7)
|
||
|
|
|
||
|
|
/* Interrupt status */
|
||
|
|
|
||
|
|
/* interrupt register 1 */
|
||
|
|
#define READY (1 << 0) /* Radio ready after powerup or reset */
|
||
|
|
#define TUNE (1 << 1) /* Tune completed */
|
||
|
|
#define SEARCH (1 << 2) /* Search completed (read FREQ) */
|
||
|
|
#define SCANNEXT (1 << 3) /* Scanning for next station */
|
||
|
|
#define SIGNAL (1 << 4) /* Signal indicator change (read SIGSTATE) */
|
||
|
|
#define INTF (1 << 5) /* Interference cnt has fallen outside range */
|
||
|
|
#define SYNC (1 << 6) /* RDS sync state change (read RDSSYNC) */
|
||
|
|
#define AUDIO (1 << 7) /* Audio Control indicator (read AUDIOIND) */
|
||
|
|
|
||
|
|
/* interrupt register 2 */
|
||
|
|
#define RDSDAT (1 << 0) /* New unread RDS data group available */
|
||
|
|
#define BLOCKB (1 << 1) /* Block-B match condition exists */
|
||
|
|
#define PROGID (1 << 2) /* Block-A or Block-C matched stored PI value*/
|
||
|
|
#define RDSPS (1 << 3) /* New RDS Program Service Table available */
|
||
|
|
#define RDSRT (1 << 4) /* New RDS Radio Text available */
|
||
|
|
#define RDSAF (1 << 5) /* New RDS AF List available */
|
||
|
|
#define TXRDSDAT (1 << 6) /* Transmitted an RDS group */
|
||
|
|
#define TXRDSDONE (1 << 7) /* RDS raw group one-shot transmit completed */
|
||
|
|
|
||
|
|
/* interrupt register 3 */
|
||
|
|
#define TRANSFER (1 << 0) /* Data transfer (XFR) completed */
|
||
|
|
#define RDSPROC (1 << 1) /* Dynamic RDS Processing complete */
|
||
|
|
#define ERROR (1 << 7) /* Err occurred.Read code to determine cause */
|
||
|
|
|
||
|
|
|
||
|
|
#define FM_TX_PWR_LVL_0 0 /* Lowest power lvl that can be set for Tx */
|
||
|
|
#define FM_TX_PWR_LVL_MAX 7 /* Max power lvl for Tx */
|
||
|
|
|
||
|
|
/* Tone Generator control value */
|
||
|
|
#define TONE_GEN_CTRL_BYTE 0x00
|
||
|
|
#define TONE_CHANNEL_EN_AND_SCALING_BYTE 0x01
|
||
|
|
#define TONE_LEFT_FREQ_BYTE 0x02
|
||
|
|
#define TONE_RIGHT_FREQ_BYTE 0x03
|
||
|
|
#define TONE_LEFT_PHASE 0x04
|
||
|
|
#define TONE_RIGHT_PHASE 0x05
|
||
|
|
|
||
|
|
#define TONE_LEFT_CH_ENABLED 0x01
|
||
|
|
#define TONE_RIGHT_CH_ENABLED 0x02
|
||
|
|
#define TONE_LEFT_RIGHT_CH_ENABLED (TONE_LEFT_CH_ENABLED\
|
||
|
|
| TONE_RIGHT_CH_ENABLED)
|
||
|
|
|
||
|
|
#define TONE_SCALING_SHIFT 0x02
|
||
|
|
|
||
|
|
/* Transfer */
|
||
|
|
enum tavarua_xfr_ctrl_t {
|
||
|
|
RDS_PS_0 = 0x01,
|
||
|
|
RDS_PS_1,
|
||
|
|
RDS_PS_2,
|
||
|
|
RDS_PS_3,
|
||
|
|
RDS_PS_4,
|
||
|
|
RDS_PS_5,
|
||
|
|
RDS_PS_6,
|
||
|
|
RDS_RT_0,
|
||
|
|
RDS_RT_1,
|
||
|
|
RDS_RT_2,
|
||
|
|
RDS_RT_3,
|
||
|
|
RDS_RT_4,
|
||
|
|
RDS_AF_0,
|
||
|
|
RDS_AF_1,
|
||
|
|
RDS_CONFIG,
|
||
|
|
RDS_TX_GROUPS,
|
||
|
|
RDS_COUNT_0,
|
||
|
|
RDS_COUNT_1,
|
||
|
|
RDS_COUNT_2,
|
||
|
|
RADIO_CONFIG,
|
||
|
|
RX_CONFIG,
|
||
|
|
RX_TIMERS,
|
||
|
|
RX_STATIONS_0,
|
||
|
|
RX_STATIONS_1,
|
||
|
|
INT_CTRL,
|
||
|
|
ERROR_CODE,
|
||
|
|
CHIPID,
|
||
|
|
CAL_DAT_0 = 0x20,
|
||
|
|
CAL_DAT_1,
|
||
|
|
CAL_DAT_2,
|
||
|
|
CAL_DAT_3,
|
||
|
|
CAL_CFG_0,
|
||
|
|
CAL_CFG_1,
|
||
|
|
DIG_INTF_0,
|
||
|
|
DIG_INTF_1,
|
||
|
|
DIG_AGC_0,
|
||
|
|
DIG_AGC_1,
|
||
|
|
DIG_AGC_2,
|
||
|
|
DIG_AUDIO_0,
|
||
|
|
DIG_AUDIO_1,
|
||
|
|
DIG_AUDIO_2,
|
||
|
|
DIG_AUDIO_3,
|
||
|
|
DIG_AUDIO_4,
|
||
|
|
DIG_RXRDS,
|
||
|
|
DIG_DCC,
|
||
|
|
DIG_SPUR,
|
||
|
|
DIG_MPXDCC,
|
||
|
|
DIG_PILOT,
|
||
|
|
DIG_DEMOD,
|
||
|
|
DIG_MOST,
|
||
|
|
DIG_TX_0,
|
||
|
|
DIG_TX_1,
|
||
|
|
PHY_TXGAIN = 0x3B,
|
||
|
|
PHY_CONFIG,
|
||
|
|
PHY_TXBLOCK,
|
||
|
|
PHY_TCB,
|
||
|
|
XFR_EXT,
|
||
|
|
XFR_PEEK_MODE = 0x40,
|
||
|
|
XFR_POKE_MODE = 0xC0,
|
||
|
|
TAVARUA_XFR_CTRL_MAX
|
||
|
|
};
|
||
|
|
|
||
|
|
enum tavarua_evt_t {
|
||
|
|
TAVARUA_EVT_RADIO_READY,
|
||
|
|
TAVARUA_EVT_TUNE_SUCC,
|
||
|
|
TAVARUA_EVT_SEEK_COMPLETE,
|
||
|
|
TAVARUA_EVT_SCAN_NEXT,
|
||
|
|
TAVARUA_EVT_NEW_RAW_RDS,
|
||
|
|
TAVARUA_EVT_NEW_RT_RDS,
|
||
|
|
TAVARUA_EVT_NEW_PS_RDS,
|
||
|
|
TAVARUA_EVT_ERROR,
|
||
|
|
TAVARUA_EVT_BELOW_TH,
|
||
|
|
TAVARUA_EVT_ABOVE_TH,
|
||
|
|
TAVARUA_EVT_STEREO,
|
||
|
|
TAVARUA_EVT_MONO,
|
||
|
|
TAVARUA_EVT_RDS_AVAIL,
|
||
|
|
TAVARUA_EVT_RDS_NOT_AVAIL,
|
||
|
|
TAVARUA_EVT_NEW_SRCH_LIST,
|
||
|
|
TAVARUA_EVT_NEW_AF_LIST,
|
||
|
|
TAVARUA_EVT_TXRDSDAT,
|
||
|
|
TAVARUA_EVT_TXRDSDONE,
|
||
|
|
TAVARUA_EVT_RADIO_DISABLED
|
||
|
|
};
|
||
|
|
|
||
|
|
enum tavarua_region_t {
|
||
|
|
TAVARUA_REGION_US,
|
||
|
|
TAVARUA_REGION_EU,
|
||
|
|
TAVARUA_REGION_JAPAN,
|
||
|
|
TAVARUA_REGION_JAPAN_WIDE,
|
||
|
|
TAVARUA_REGION_OTHER
|
||
|
|
};
|
||
|
|
|
||
|
|
enum {
|
||
|
|
ONE_BYTE = 1,
|
||
|
|
TWO_BYTE,
|
||
|
|
THREE_BYTE,
|
||
|
|
FOUR_BYTE,
|
||
|
|
FIVE_BYTE,
|
||
|
|
SIX_BYTE,
|
||
|
|
SEVEN_BYTE,
|
||
|
|
EIGHT_BYTE,
|
||
|
|
NINE_BYTE,
|
||
|
|
TEN_BYTE,
|
||
|
|
ELEVEN_BYTE,
|
||
|
|
TWELVE_BYTE,
|
||
|
|
THIRTEEN_BYTE
|
||
|
|
};
|
||
|
|
|
||
|
|
#define XFR_READ (0)
|
||
|
|
#define XFR_WRITE (1)
|
||
|
|
#define XFR_MODE_OFFSET (0)
|
||
|
|
#define XFR_ADDR_MSB_OFFSET (1)
|
||
|
|
#define XFR_ADDR_LSB_OFFSET (2)
|
||
|
|
#define XFR_DATA_OFFSET (3)
|
||
|
|
#define SPUR_DATA_SIZE (3)
|
||
|
|
#define MAX_SPUR_FREQ_LIMIT (30)
|
||
|
|
#define READ_COMPLETE (0x20)
|
||
|
|
#define SPUR_TABLE_ADDR (0x0BB7)
|
||
|
|
#define SPUR_TABLE_START_ADDR (SPUR_TABLE_ADDR + 1)
|
||
|
|
#define XFR_PEEK_COMPLETE (XFR_PEEK_MODE | READ_COMPLETE)
|
||
|
|
#define XFR_POKE_COMPLETE (XFR_POKE_MODE)
|
||
|
|
#define TUNE_MULT (16)
|
||
|
|
#define ADJ_CHANNEL_KHZ (50)
|
||
|
|
#define MPX_DCC_UPPER_LIMIT (20000)
|
||
|
|
#define MPX_DCC_LIMIT (12566)
|
||
|
|
#define INVALID_CHANNEL (0)
|
||
|
|
#define VALID_CHANNEL (1)
|
||
|
|
|
||
|
|
#define COMPUTE_SPUR(val) ((((val) - (76000)) / (50)))
|
||
|
|
#define GET_FREQ(val, bit) ((bit == 1) ? ((val) >> 8) : ((val) & 0xFF))
|
||
|
|
|
||
|
|
struct fm_spur_data {
|
||
|
|
int freq[MAX_SPUR_FREQ_LIMIT];
|
||
|
|
__s8 rmssi[MAX_SPUR_FREQ_LIMIT];
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
struct fm_def_data_wr_req {
|
||
|
|
__u8 mode;
|
||
|
|
__u8 length;
|
||
|
|
__u8 data[XFR_REG_NUM];
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
enum Internal_tone_gen_vals {
|
||
|
|
ONE_KHZ_LR_EQUA_0DBFS = 1,
|
||
|
|
ONE_KHZ_LEFTONLY_EQUA_0DBFS,
|
||
|
|
ONE_KHZ_RIGHTONLY_EQUA_0DBFS,
|
||
|
|
ONE_KHZ_LR_EQUA_l8DBFS,
|
||
|
|
FIFTEEN_KHZ_LR_EQUA_l8DBFS
|
||
|
|
};
|
||
|
|
|
||
|
|
enum Tone_scaling_indexes {
|
||
|
|
TONE_SCALE_IND_0,
|
||
|
|
TONE_SCALE_IND_1,
|
||
|
|
TONE_SCALE_IND_2,
|
||
|
|
TONE_SCALE_IND_3,
|
||
|
|
TONE_SCALE_IND_4,
|
||
|
|
TONE_SCALE_IND_5,
|
||
|
|
TONE_SCALE_IND_6,
|
||
|
|
TONE_SCALE_IND_7,
|
||
|
|
TONE_SCALE_IND_8,
|
||
|
|
TONE_SCALE_IND_9,
|
||
|
|
TONE_SCALE_IND_10,
|
||
|
|
TONE_SCALE_IND_11,
|
||
|
|
TONE_SCALE_IND_12
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif /* __LINUX_TAVARUA_H */
|