277 lines
8.8 KiB
C
277 lines
8.8 KiB
C
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/*
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* Copyright (c) 2004-2011 Atheros Communications Inc.
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* Copyright (c) 2011 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef HIF_H
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#define HIF_H
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#include "common.h"
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#include "core.h"
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#include <linux/scatterlist.h>
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#define BUS_REQUEST_MAX_NUM 64
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#define HIF_MBOX_BLOCK_SIZE 128
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#define HIF_MBOX0_BLOCK_SIZE 1
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#define HIF_DMA_BUFFER_SIZE (32 * 1024)
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#define CMD53_FIXED_ADDRESS 1
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#define CMD53_INCR_ADDRESS 2
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#define MAX_SCATTER_REQUESTS 4
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#define MAX_SCATTER_ENTRIES_PER_REQ 16
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#define MAX_SCATTER_REQ_TRANSFER_SIZE (32 * 1024)
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#define MANUFACTURER_ID_AR6003_BASE 0x300
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#define MANUFACTURER_ID_AR6004_BASE 0x400
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/* SDIO manufacturer ID and Codes */
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#define MANUFACTURER_ID_ATH6KL_BASE_MASK 0xFF00
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#define MANUFACTURER_CODE 0x271 /* Atheros */
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/* Mailbox address in SDIO address space */
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#define HIF_MBOX_BASE_ADDR 0x800
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#define HIF_MBOX_WIDTH 0x800
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#define HIF_MBOX_END_ADDR (HTC_MAILBOX_NUM_MAX * HIF_MBOX_WIDTH - 1)
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/* version 1 of the chip has only a 12K extended mbox range */
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#define HIF_MBOX0_EXT_BASE_ADDR 0x4000
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#define HIF_MBOX0_EXT_WIDTH (12*1024)
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/* GMBOX addresses */
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#define HIF_GMBOX_BASE_ADDR 0x7000
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#define HIF_GMBOX_WIDTH 0x4000
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/* interrupt mode register */
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#define CCCR_SDIO_IRQ_MODE_REG 0xF0
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/* mode to enable special 4-bit interrupt assertion without clock */
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#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0)
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/* HTC runs over mailbox 0 */
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#define HTC_MAILBOX 0
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#define ATH6KL_TARGET_DEBUG_INTR_MASK 0x01
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/* FIXME: are these duplicates with MAX_SCATTER_ values in hif.h? */
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#define ATH6KL_SCATTER_ENTRIES_PER_REQ 16
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#define ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER (16 * 1024)
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#define ATH6KL_SCATTER_REQS 4
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#define ATH6KL_HIF_COMMUNICATION_TIMEOUT 1000
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struct bus_request {
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struct list_head list;
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/* request data */
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u32 address;
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u8 *buffer;
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u32 length;
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u32 request;
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struct htc_packet *packet;
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int status;
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/* this is a scatter request */
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struct hif_scatter_req *scat_req;
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};
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/* direction of transfer (read/write) */
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#define HIF_READ 0x00000001
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#define HIF_WRITE 0x00000002
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#define HIF_DIR_MASK (HIF_READ | HIF_WRITE)
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/*
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* emode - This indicates the whether the command is to be executed in a
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* blocking or non-blocking fashion (HIF_SYNCHRONOUS/
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* HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
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* implemented using the asynchronous mode allowing the the bus
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* driver to indicate the completion of operation through the
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* registered callback routine. The requirement primarily comes
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* from the contexts these operations get called from (a driver's
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* transmit context or the ISR context in case of receive).
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* Support for both of these modes is essential.
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*/
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#define HIF_SYNCHRONOUS 0x00000010
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#define HIF_ASYNCHRONOUS 0x00000020
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#define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
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/*
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* dmode - An interface may support different kinds of commands based on
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* the tradeoff between the amount of data it can carry and the
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* setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
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* HIF_BLOCK_BASIS). In case of latter, the data is rounded off
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* to the nearest block size by padding. The size of the block is
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* configurable at compile time using the HIF_BLOCK_SIZE and is
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* negotiated with the target during initialization after the
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* ATH6KL interrupts are enabled.
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*/
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#define HIF_BYTE_BASIS 0x00000040
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#define HIF_BLOCK_BASIS 0x00000080
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#define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
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/*
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* amode - This indicates if the address has to be incremented on ATH6KL
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* after every read/write operation (HIF?FIXED_ADDRESS/
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* HIF_INCREMENTAL_ADDRESS).
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*/
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#define HIF_FIXED_ADDRESS 0x00000100
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#define HIF_INCREMENTAL_ADDRESS 0x00000200
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#define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
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#define HIF_WR_ASYNC_BYTE_INC \
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(HIF_WRITE | HIF_ASYNCHRONOUS | \
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HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
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#define HIF_WR_ASYNC_BLOCK_INC \
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(HIF_WRITE | HIF_ASYNCHRONOUS | \
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HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
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#define HIF_WR_SYNC_BYTE_FIX \
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(HIF_WRITE | HIF_SYNCHRONOUS | \
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HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
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#define HIF_WR_SYNC_BYTE_INC \
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(HIF_WRITE | HIF_SYNCHRONOUS | \
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HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
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#define HIF_WR_SYNC_BLOCK_INC \
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(HIF_WRITE | HIF_SYNCHRONOUS | \
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HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
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#define HIF_RD_SYNC_BYTE_INC \
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(HIF_READ | HIF_SYNCHRONOUS | \
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HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
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#define HIF_RD_SYNC_BYTE_FIX \
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(HIF_READ | HIF_SYNCHRONOUS | \
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HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
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#define HIF_RD_ASYNC_BLOCK_FIX \
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(HIF_READ | HIF_ASYNCHRONOUS | \
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HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
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#define HIF_RD_SYNC_BLOCK_FIX \
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(HIF_READ | HIF_SYNCHRONOUS | \
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HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
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struct hif_scatter_item {
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u8 *buf;
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int len;
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struct htc_packet *packet;
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};
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struct hif_scatter_req {
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struct list_head list;
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/* address for the read/write operation */
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u32 addr;
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/* request flags */
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u32 req;
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/* total length of entire transfer */
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u32 len;
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bool virt_scat;
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void (*complete) (struct htc_target *, struct hif_scatter_req *);
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int status;
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int scat_entries;
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struct bus_request *busrequest;
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struct scatterlist *sgentries;
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/* bounce buffer for upper layers to copy to/from */
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u8 *virt_dma_buf;
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struct hif_scatter_item scat_list[1];
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u32 scat_q_depth;
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};
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struct ath6kl_irq_proc_registers {
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u8 host_int_status;
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u8 cpu_int_status;
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u8 error_int_status;
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u8 counter_int_status;
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u8 mbox_frame;
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u8 rx_lkahd_valid;
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u8 host_int_status2;
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u8 gmbox_rx_avail;
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__le32 rx_lkahd[2];
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__le32 rx_gmbox_lkahd_alias[2];
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} __packed;
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struct ath6kl_irq_enable_reg {
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u8 int_status_en;
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u8 cpu_int_status_en;
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u8 err_int_status_en;
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u8 cntr_int_status_en;
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} __packed;
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struct ath6kl_device {
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/* protects irq_proc_reg and irq_en_reg below */
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spinlock_t lock;
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struct ath6kl_irq_proc_registers irq_proc_reg;
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struct ath6kl_irq_enable_reg irq_en_reg;
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struct htc_target *htc_cnxt;
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struct ath6kl *ar;
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};
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struct ath6kl_hif_ops {
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int (*read_write_sync)(struct ath6kl *ar, u32 addr, u8 *buf,
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u32 len, u32 request);
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int (*write_async)(struct ath6kl *ar, u32 address, u8 *buffer,
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u32 length, u32 request, struct htc_packet *packet);
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void (*irq_enable)(struct ath6kl *ar);
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void (*irq_disable)(struct ath6kl *ar);
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struct hif_scatter_req *(*scatter_req_get)(struct ath6kl *ar);
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void (*scatter_req_add)(struct ath6kl *ar,
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struct hif_scatter_req *s_req);
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int (*enable_scatter)(struct ath6kl *ar);
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int (*scat_req_rw) (struct ath6kl *ar,
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struct hif_scatter_req *scat_req);
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void (*cleanup_scatter)(struct ath6kl *ar);
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int (*suspend)(struct ath6kl *ar, struct cfg80211_wowlan *wow);
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int (*resume)(struct ath6kl *ar);
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int (*diag_read32)(struct ath6kl *ar, u32 address, u32 *value);
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int (*diag_write32)(struct ath6kl *ar, u32 address, __le32 value);
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int (*bmi_read)(struct ath6kl *ar, u8 *buf, u32 len);
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int (*bmi_write)(struct ath6kl *ar, u8 *buf, u32 len);
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int (*power_on)(struct ath6kl *ar);
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int (*power_off)(struct ath6kl *ar);
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void (*stop)(struct ath6kl *ar);
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};
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int ath6kl_hif_setup(struct ath6kl_device *dev);
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int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev);
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int ath6kl_hif_mask_intrs(struct ath6kl_device *dev);
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int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev,
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u32 *lk_ahd, int timeout);
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int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx);
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int ath6kl_hif_disable_intrs(struct ath6kl_device *dev);
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int ath6kl_hif_rw_comp_handler(void *context, int status);
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int ath6kl_hif_intr_bh_handler(struct ath6kl *ar);
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/* Scatter Function and Definitions */
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int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev,
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struct hif_scatter_req *scat_req, bool read);
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#endif
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