456 lines
13 KiB
C
456 lines
13 KiB
C
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/*******************************************************************************
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Intel(R) Gigabit Ethernet Linux driver
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Copyright(c) 2007-2012 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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/* Linux PRO/1000 Ethernet Driver main header file */
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#ifndef _IGB_H_
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#define _IGB_H_
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#include "e1000_mac.h"
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#include "e1000_82575.h"
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#include <linux/clocksource.h>
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#include <linux/timecompare.h>
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#include <linux/net_tstamp.h>
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#include <linux/bitops.h>
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#include <linux/if_vlan.h>
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struct igb_adapter;
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/* Interrupt defines */
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#define IGB_START_ITR 648 /* ~6000 ints/sec */
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#define IGB_4K_ITR 980
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#define IGB_20K_ITR 196
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#define IGB_70K_ITR 56
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/* TX/RX descriptor defines */
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#define IGB_DEFAULT_TXD 256
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#define IGB_DEFAULT_TX_WORK 128
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#define IGB_MIN_TXD 80
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#define IGB_MAX_TXD 4096
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#define IGB_DEFAULT_RXD 256
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#define IGB_MIN_RXD 80
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#define IGB_MAX_RXD 4096
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#define IGB_DEFAULT_ITR 3 /* dynamic */
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#define IGB_MAX_ITR_USECS 10000
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#define IGB_MIN_ITR_USECS 10
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#define NON_Q_VECTORS 1
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#define MAX_Q_VECTORS 8
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/* Transmit and receive queues */
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#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
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(hw->mac.type > e1000_82575 ? 8 : 4))
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#define IGB_MAX_TX_QUEUES 16
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#define IGB_MAX_VF_MC_ENTRIES 30
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#define IGB_MAX_VF_FUNCTIONS 8
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#define IGB_MAX_VFTA_ENTRIES 128
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#define IGB_82576_VF_DEV_ID 0x10CA
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#define IGB_I350_VF_DEV_ID 0x1520
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struct vf_data_storage {
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unsigned char vf_mac_addresses[ETH_ALEN];
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u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
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u16 num_vf_mc_hashes;
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u16 vlans_enabled;
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u32 flags;
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unsigned long last_nack;
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u16 pf_vlan; /* When set, guest VLAN config not allowed. */
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u16 pf_qos;
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u16 tx_rate;
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struct pci_dev *vfdev;
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};
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#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
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#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
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#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
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#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
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/* RX descriptor control thresholds.
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* PTHRESH - MAC will consider prefetch if it has fewer than this number of
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* descriptors available in its onboard memory.
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* Setting this to 0 disables RX descriptor prefetch.
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* HTHRESH - MAC will only prefetch if there are at least this many descriptors
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* available in host memory.
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* If PTHRESH is 0, this should also be 0.
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* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
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* descriptors until either it has this many to write back, or the
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* ITR timer expires.
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*/
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#define IGB_RX_PTHRESH 8
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#define IGB_RX_HTHRESH 8
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#define IGB_TX_PTHRESH 8
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#define IGB_TX_HTHRESH 1
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#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
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adapter->msix_entries) ? 1 : 4)
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#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
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adapter->msix_entries) ? 1 : 16)
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/* this is the size past which hardware will drop packets when setting LPE=0 */
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#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
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/* Supported Rx Buffer Sizes */
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#define IGB_RXBUFFER_512 512
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#define IGB_RXBUFFER_16384 16384
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#define IGB_RX_HDR_LEN IGB_RXBUFFER_512
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/* How many Tx Descriptors do we need to call netif_wake_queue ? */
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#define IGB_TX_QUEUE_WAKE 16
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/* How many Rx Buffers do we bundle into one write to the hardware ? */
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#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
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#define AUTO_ALL_MODES 0
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#define IGB_EEPROM_APME 0x0400
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#ifndef IGB_MASTER_SLAVE
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/* Switch to override PHY master/slave setting */
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#define IGB_MASTER_SLAVE e1000_ms_hw_default
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#endif
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#define IGB_MNG_VLAN_NONE -1
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#define IGB_TX_FLAGS_CSUM 0x00000001
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#define IGB_TX_FLAGS_VLAN 0x00000002
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#define IGB_TX_FLAGS_TSO 0x00000004
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#define IGB_TX_FLAGS_IPV4 0x00000008
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#define IGB_TX_FLAGS_TSTAMP 0x00000010
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#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
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#define IGB_TX_FLAGS_VLAN_SHIFT 16
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/* wrapper around a pointer to a socket buffer,
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* so a DMA handle can be stored along with the buffer */
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struct igb_tx_buffer {
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union e1000_adv_tx_desc *next_to_watch;
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unsigned long time_stamp;
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struct sk_buff *skb;
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unsigned int bytecount;
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u16 gso_segs;
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__be16 protocol;
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dma_addr_t dma;
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u32 length;
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u32 tx_flags;
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};
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struct igb_rx_buffer {
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struct sk_buff *skb;
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dma_addr_t dma;
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struct page *page;
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dma_addr_t page_dma;
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u32 page_offset;
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};
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struct igb_tx_queue_stats {
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u64 packets;
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u64 bytes;
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u64 restart_queue;
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u64 restart_queue2;
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};
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struct igb_rx_queue_stats {
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u64 packets;
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u64 bytes;
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u64 drops;
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u64 csum_err;
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u64 alloc_failed;
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};
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struct igb_ring_container {
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struct igb_ring *ring; /* pointer to linked list of rings */
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_packets; /* total packets processed this int */
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u16 work_limit; /* total work allowed per interrupt */
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u8 count; /* total number of rings in vector */
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u8 itr; /* current ITR setting for ring */
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};
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struct igb_q_vector {
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struct igb_adapter *adapter; /* backlink */
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int cpu; /* CPU for DCA */
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u32 eims_value; /* EIMS mask value */
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struct igb_ring_container rx, tx;
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struct napi_struct napi;
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int numa_node;
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u16 itr_val;
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u8 set_itr;
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void __iomem *itr_register;
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char name[IFNAMSIZ + 9];
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};
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struct igb_ring {
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struct igb_q_vector *q_vector; /* backlink to q_vector */
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struct net_device *netdev; /* back pointer to net_device */
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struct device *dev; /* device pointer for dma mapping */
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union { /* array of buffer info structs */
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struct igb_tx_buffer *tx_buffer_info;
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struct igb_rx_buffer *rx_buffer_info;
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};
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void *desc; /* descriptor ring memory */
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unsigned long flags; /* ring specific flags */
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void __iomem *tail; /* pointer to ring tail register */
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u16 count; /* number of desc. in the ring */
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u8 queue_index; /* logical index of the ring*/
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u8 reg_idx; /* physical index of the ring */
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u32 size; /* length of desc. ring in bytes */
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/* everything past this point are written often */
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u16 next_to_clean ____cacheline_aligned_in_smp;
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u16 next_to_use;
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union {
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/* TX */
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struct {
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struct igb_tx_queue_stats tx_stats;
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struct u64_stats_sync tx_syncp;
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struct u64_stats_sync tx_syncp2;
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};
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/* RX */
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struct {
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struct igb_rx_queue_stats rx_stats;
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struct u64_stats_sync rx_syncp;
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};
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};
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/* Items past this point are only used during ring alloc / free */
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dma_addr_t dma; /* phys address of the ring */
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int numa_node; /* node to alloc ring memory on */
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};
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enum e1000_ring_flags_t {
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IGB_RING_FLAG_RX_SCTP_CSUM,
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IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
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IGB_RING_FLAG_TX_CTX_IDX,
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IGB_RING_FLAG_TX_DETECT_HANG
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};
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#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
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#define IGB_RX_DESC(R, i) \
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(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
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#define IGB_TX_DESC(R, i) \
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(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
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#define IGB_TX_CTXTDESC(R, i) \
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(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
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/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
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static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
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const u32 stat_err_bits)
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{
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return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
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}
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/* igb_desc_unused - calculate if we have unused descriptors */
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static inline int igb_desc_unused(struct igb_ring *ring)
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{
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if (ring->next_to_clean > ring->next_to_use)
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return ring->next_to_clean - ring->next_to_use - 1;
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return ring->count + ring->next_to_clean - ring->next_to_use - 1;
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}
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/* board specific private data structure */
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struct igb_adapter {
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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struct net_device *netdev;
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unsigned long state;
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unsigned int flags;
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unsigned int num_q_vectors;
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struct msix_entry *msix_entries;
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/* Interrupt Throttle Rate */
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u32 rx_itr_setting;
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u32 tx_itr_setting;
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u16 tx_itr;
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u16 rx_itr;
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/* TX */
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u16 tx_work_limit;
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u32 tx_timeout_count;
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int num_tx_queues;
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struct igb_ring *tx_ring[16];
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/* RX */
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int num_rx_queues;
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struct igb_ring *rx_ring[16];
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u32 max_frame_size;
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u32 min_frame_size;
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struct timer_list watchdog_timer;
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struct timer_list phy_info_timer;
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u16 mng_vlan_id;
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u32 bd_number;
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u32 wol;
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u32 en_mng_pt;
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u16 link_speed;
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u16 link_duplex;
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struct work_struct reset_task;
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struct work_struct watchdog_task;
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bool fc_autoneg;
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u8 tx_timeout_factor;
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struct timer_list blink_timer;
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unsigned long led_status;
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/* OS defined structs */
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struct pci_dev *pdev;
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struct cyclecounter cycles;
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struct timecounter clock;
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struct timecompare compare;
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struct hwtstamp_config hwtstamp_config;
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spinlock_t stats64_lock;
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struct rtnl_link_stats64 stats64;
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/* structs defined in e1000_hw.h */
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struct e1000_hw hw;
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struct e1000_hw_stats stats;
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struct e1000_phy_info phy_info;
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struct e1000_phy_stats phy_stats;
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u32 test_icr;
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struct igb_ring test_tx_ring;
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struct igb_ring test_rx_ring;
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int msg_enable;
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struct igb_q_vector *q_vector[MAX_Q_VECTORS];
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u32 eims_enable_mask;
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u32 eims_other;
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/* to not mess up cache alignment, always add to the bottom */
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u32 eeprom_wol;
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u16 tx_ring_count;
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u16 rx_ring_count;
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unsigned int vfs_allocated_count;
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struct vf_data_storage *vf_data;
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int vf_rate_link_speed;
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u32 rss_queues;
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u32 wvbr;
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int node;
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u32 *shadow_vfta;
|
||
|
|
};
|
||
|
|
|
||
|
|
#define IGB_FLAG_HAS_MSI (1 << 0)
|
||
|
|
#define IGB_FLAG_DCA_ENABLED (1 << 1)
|
||
|
|
#define IGB_FLAG_QUAD_PORT_A (1 << 2)
|
||
|
|
#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
|
||
|
|
#define IGB_FLAG_DMAC (1 << 4)
|
||
|
|
|
||
|
|
/* DMA Coalescing defines */
|
||
|
|
#define IGB_MIN_TXPBSIZE 20408
|
||
|
|
#define IGB_TX_BUF_4096 4096
|
||
|
|
#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
|
||
|
|
|
||
|
|
#define IGB_82576_TSYNC_SHIFT 19
|
||
|
|
#define IGB_82580_TSYNC_SHIFT 24
|
||
|
|
#define IGB_TS_HDR_LEN 16
|
||
|
|
enum e1000_state_t {
|
||
|
|
__IGB_TESTING,
|
||
|
|
__IGB_RESETTING,
|
||
|
|
__IGB_DOWN
|
||
|
|
};
|
||
|
|
|
||
|
|
enum igb_boards {
|
||
|
|
board_82575,
|
||
|
|
};
|
||
|
|
|
||
|
|
extern char igb_driver_name[];
|
||
|
|
extern char igb_driver_version[];
|
||
|
|
|
||
|
|
extern int igb_up(struct igb_adapter *);
|
||
|
|
extern void igb_down(struct igb_adapter *);
|
||
|
|
extern void igb_reinit_locked(struct igb_adapter *);
|
||
|
|
extern void igb_reset(struct igb_adapter *);
|
||
|
|
extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
|
||
|
|
extern int igb_setup_tx_resources(struct igb_ring *);
|
||
|
|
extern int igb_setup_rx_resources(struct igb_ring *);
|
||
|
|
extern void igb_free_tx_resources(struct igb_ring *);
|
||
|
|
extern void igb_free_rx_resources(struct igb_ring *);
|
||
|
|
extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
|
||
|
|
extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
|
||
|
|
extern void igb_setup_tctl(struct igb_adapter *);
|
||
|
|
extern void igb_setup_rctl(struct igb_adapter *);
|
||
|
|
extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
|
||
|
|
extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
|
||
|
|
struct igb_tx_buffer *);
|
||
|
|
extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
|
||
|
|
extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
|
||
|
|
extern bool igb_has_link(struct igb_adapter *adapter);
|
||
|
|
extern void igb_set_ethtool_ops(struct net_device *);
|
||
|
|
extern void igb_power_up_link(struct igb_adapter *);
|
||
|
|
|
||
|
|
static inline s32 igb_reset_phy(struct e1000_hw *hw)
|
||
|
|
{
|
||
|
|
if (hw->phy.ops.reset)
|
||
|
|
return hw->phy.ops.reset(hw);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
|
||
|
|
{
|
||
|
|
if (hw->phy.ops.read_reg)
|
||
|
|
return hw->phy.ops.read_reg(hw, offset, data);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
|
||
|
|
{
|
||
|
|
if (hw->phy.ops.write_reg)
|
||
|
|
return hw->phy.ops.write_reg(hw, offset, data);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline s32 igb_get_phy_info(struct e1000_hw *hw)
|
||
|
|
{
|
||
|
|
if (hw->phy.ops.get_phy_info)
|
||
|
|
return hw->phy.ops.get_phy_info(hw);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
|
||
|
|
{
|
||
|
|
return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* _IGB_H_ */
|