266 lines
7.6 KiB
C
266 lines
7.6 KiB
C
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/*
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* The SH64 TLB miss.
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*
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* Original code from fault.c
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* Copyright (C) 2000, 2001 Paolo Alberelli
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*
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* Fast PTE->TLB refill path
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* Copyright (C) 2003 Richard.Curnow@superh.com
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*
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* IMPORTANT NOTES :
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* The do_fast_page_fault function is called from a context in entry.S
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* where very few registers have been saved. In particular, the code in
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* this file must be compiled not to use ANY caller-save registers that
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* are not part of the restricted save set. Also, it means that code in
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* this file must not make calls to functions elsewhere in the kernel, or
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* else the excepting context will see corruption in its caller-save
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* registers. Plus, the entry.S save area is non-reentrant, so this code
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* has to run with SR.BL==1, i.e. no interrupts taken inside it and panic
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* on any exception.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <asm/tlb.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <cpu/registers.h>
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/* Callable from fault.c, so not static */
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inline void __do_tlb_refill(unsigned long address,
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unsigned long long is_text_not_data, pte_t *pte)
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{
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unsigned long long ptel;
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unsigned long long pteh=0;
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struct tlb_info *tlbp;
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unsigned long long next;
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/* Get PTEL first */
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ptel = pte_val(*pte);
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/*
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* Set PTEH register
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*/
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pteh = neff_sign_extend(address & MMU_VPN_MASK);
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/* Set the ASID. */
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pteh |= get_asid() << PTEH_ASID_SHIFT;
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pteh |= PTEH_VALID;
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/* Set PTEL register, set_pte has performed the sign extension */
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ptel &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
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tlbp = is_text_not_data ? &(cpu_data->itlb) : &(cpu_data->dtlb);
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next = tlbp->next;
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__flush_tlb_slot(next);
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asm volatile ("putcfg %0,1,%2\n\n\t"
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"putcfg %0,0,%1\n"
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: : "r" (next), "r" (pteh), "r" (ptel) );
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next += TLB_STEP;
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if (next > tlbp->last) next = tlbp->first;
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tlbp->next = next;
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}
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static int handle_vmalloc_fault(struct mm_struct *mm,
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unsigned long protection_flags,
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unsigned long long textaccess,
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unsigned long address)
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{
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pgd_t *dir;
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pud_t *pud;
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pmd_t *pmd;
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static pte_t *pte;
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pte_t entry;
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dir = pgd_offset_k(address);
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pud = pud_offset(dir, address);
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if (pud_none_or_clear_bad(pud))
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return 0;
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pmd = pmd_offset(pud, address);
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if (pmd_none_or_clear_bad(pmd))
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return 0;
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pte = pte_offset_kernel(pmd, address);
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entry = *pte;
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if (pte_none(entry) || !pte_present(entry))
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return 0;
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if ((pte_val(entry) & protection_flags) != protection_flags)
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return 0;
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__do_tlb_refill(address, textaccess, pte);
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return 1;
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}
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static int handle_tlbmiss(struct mm_struct *mm,
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unsigned long long protection_flags,
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unsigned long long textaccess,
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unsigned long address)
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{
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pgd_t *dir;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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pte_t entry;
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/* NB. The PGD currently only contains a single entry - there is no
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page table tree stored for the top half of the address space since
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virtual pages in that region should never be mapped in user mode.
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(In kernel mode, the only things in that region are the 512Mb super
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page (locked in), and vmalloc (modules) + I/O device pages (handled
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by handle_vmalloc_fault), so no PGD for the upper half is required
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by kernel mode either).
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See how mm->pgd is allocated and initialised in pgd_alloc to see why
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the next test is necessary. - RPC */
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if (address >= (unsigned long) TASK_SIZE)
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/* upper half - never has page table entries. */
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return 0;
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dir = pgd_offset(mm, address);
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if (pgd_none(*dir) || !pgd_present(*dir))
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return 0;
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if (!pgd_present(*dir))
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return 0;
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pud = pud_offset(dir, address);
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if (pud_none(*pud) || !pud_present(*pud))
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return 0;
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pmd = pmd_offset(pud, address);
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if (pmd_none(*pmd) || !pmd_present(*pmd))
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return 0;
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pte = pte_offset_kernel(pmd, address);
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entry = *pte;
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if (pte_none(entry) || !pte_present(entry))
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return 0;
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/*
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* If the page doesn't have sufficient protection bits set to
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* service the kind of fault being handled, there's not much
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* point doing the TLB refill. Punt the fault to the general
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* handler.
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*/
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if ((pte_val(entry) & protection_flags) != protection_flags)
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return 0;
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__do_tlb_refill(address, textaccess, pte);
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return 1;
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}
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/*
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* Put all this information into one structure so that everything is just
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* arithmetic relative to a single base address. This reduces the number
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* of movi/shori pairs needed just to load addresses of static data.
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*/
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struct expevt_lookup {
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unsigned short protection_flags[8];
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unsigned char is_text_access[8];
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unsigned char is_write_access[8];
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};
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#define PRU (1<<9)
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#define PRW (1<<8)
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#define PRX (1<<7)
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#define PRR (1<<6)
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#define DIRTY (_PAGE_DIRTY | _PAGE_ACCESSED)
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#define YOUNG (_PAGE_ACCESSED)
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/* Sized as 8 rather than 4 to allow checking the PTE's PRU bit against whether
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the fault happened in user mode or privileged mode. */
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static struct expevt_lookup expevt_lookup_table = {
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.protection_flags = {PRX, PRX, 0, 0, PRR, PRR, PRW, PRW},
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.is_text_access = {1, 1, 0, 0, 0, 0, 0, 0}
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};
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/*
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This routine handles page faults that can be serviced just by refilling a
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TLB entry from an existing page table entry. (This case represents a very
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large majority of page faults.) Return 1 if the fault was successfully
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handled. Return 0 if the fault could not be handled. (This leads into the
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general fault handling in fault.c which deals with mapping file-backed
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pages, stack growth, segmentation faults, swapping etc etc)
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*/
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asmlinkage int do_fast_page_fault(unsigned long long ssr_md,
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unsigned long long expevt,
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unsigned long address)
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{
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struct task_struct *tsk;
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struct mm_struct *mm;
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unsigned long long textaccess;
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unsigned long long protection_flags;
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unsigned long long index;
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unsigned long long expevt4;
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/* The next few lines implement a way of hashing EXPEVT into a
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* small array index which can be used to lookup parameters
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* specific to the type of TLBMISS being handled.
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*
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* Note:
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* ITLBMISS has EXPEVT==0xa40
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* RTLBMISS has EXPEVT==0x040
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* WTLBMISS has EXPEVT==0x060
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*/
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expevt4 = (expevt >> 4);
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/* TODO : xor ssr_md into this expression too. Then we can check
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* that PRU is set when it needs to be. */
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index = expevt4 ^ (expevt4 >> 5);
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index &= 7;
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protection_flags = expevt_lookup_table.protection_flags[index];
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textaccess = expevt_lookup_table.is_text_access[index];
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/* SIM
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* Note this is now called with interrupts still disabled
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* This is to cope with being called for a missing IO port
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* address with interrupts disabled. This should be fixed as
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* soon as we have a better 'fast path' miss handler.
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*
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* Plus take care how you try and debug this stuff.
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* For example, writing debug data to a port which you
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* have just faulted on is not going to work.
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*/
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tsk = current;
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mm = tsk->mm;
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if ((address >= VMALLOC_START && address < VMALLOC_END) ||
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(address >= IOBASE_VADDR && address < IOBASE_END)) {
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if (ssr_md)
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/*
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* Process-contexts can never have this address
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* range mapped
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*/
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if (handle_vmalloc_fault(mm, protection_flags,
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textaccess, address))
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return 1;
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} else if (!in_interrupt() && mm) {
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if (handle_tlbmiss(mm, protection_flags, textaccess, address))
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return 1;
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}
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return 0;
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}
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