118 lines
3.4 KiB
C
118 lines
3.4 KiB
C
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#ifndef __MACH_SH2007_H
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#define __MACH_SH2007_H
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#define CS5BCR 0xff802050
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#define CS5WCR 0xff802058
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#define CS5PCR 0xff802070
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#define BUS_SZ8 1
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#define BUS_SZ16 2
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#define BUS_SZ32 3
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#define PCMCIA_IODYN 1
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#define PCMCIA_ATA 0
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#define PCMCIA_IO8 2
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#define PCMCIA_IO16 3
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#define PCMCIA_COMM8 4
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#define PCMCIA_COMM16 5
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#define PCMCIA_ATTR8 6
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#define PCMCIA_ATTR16 7
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#define TYPE_SRAM 0
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#define TYPE_PCMCIA 4
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/* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
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#define IWW5 0
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#define IWW6 3
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/* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
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#define IWRWD5 2
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#define IWRWD6 2
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/* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
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#define IWRWS5 2
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#define IWRWS6 2
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/* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
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#define IWRRD5 2
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#define IWRRD6 2
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/* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
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#define IWRRS5 0
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#define IWRRS6 2
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/* burst count (0-3:4,8,16,32) */
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#define BST5 0
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#define BST6 0
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/* bus size */
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#define SZ5 BUS_SZ16
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#define SZ6 BUS_SZ16
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/* RD hold for SRAM (0-1:0,1) */
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#define RDSPL5 0
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#define RDSPL6 0
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/* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
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#define BW5 0
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#define BW6 0
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/* Multiplex (0-1:0,1) */
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#define MPX5 0
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#define MPX6 0
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/* device type */
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#define TYPE5 TYPE_PCMCIA
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#define TYPE6 TYPE_PCMCIA
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/* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
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#define ADS5 0
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#define ADS6 0
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/* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
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#define ADH5 0
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#define ADH6 0
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/* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
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#define RDS5 0
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#define RDS6 0
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/* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
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#define RDH5 0
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#define RDH6 0
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/* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
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#define WTS5 0
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#define WTS6 0
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/* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
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#define WTH5 0
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#define WTH6 0
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/* BS hold (0-1:1,2) */
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#define BSH5 0
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#define BSH6 0
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/* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
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#define IW5 6 /* 60ns PIO mode 4 */
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#define IW6 15 /* 250ns */
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#define SAA5 PCMCIA_IODYN /* IDE area b4000000-b5ffffff */
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#define SAB5 PCMCIA_IODYN /* CF area b6000000-b7ffffff */
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#define PCWA5 0 /* additional wait A (0-3:0,15,30,50) */
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#define PCWB5 0 /* additional wait B (0-3:0,15,30,50) */
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/* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
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#define PCIW5 12
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/* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */
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#define TEDA5 2
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/* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */
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#define TEDB5 4
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/* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */
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#define TEHA5 2
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/* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */
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#define TEHB5 3
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#define CS5BCR_D ((IWW5<<28)|(IWRWD5<<24)|(IWRWS5<<20)| \
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(IWRRD5<<16)|(IWRRS5<<12)|(BST5<<10)| \
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(SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5)
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#define CS5WCR_D ((ADS5<<28)|(ADH5<<24)|(RDS5<<20)| \
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(RDH5<<16)|(WTS5<<12)|(WTH5<<8)|(BSH5<<4)|IW5)
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#define CS5PCR_D ((SAA5<<28)|(SAB5<<24)|(PCWA5<<22)| \
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(PCWB5<<20)|(PCIW5<<16)|(TEDA5<<12)| \
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(TEDB5<<8)|(TEHA5<<4)|TEHB5)
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#define SMC0_BASE 0xb0800000 /* eth0 */
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#define SMC1_BASE 0xb0900000 /* eth1 */
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#define CF_BASE 0xb6100000 /* Compact Flash (I/O area) */
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#define IDE_BASE 0xb4000000 /* IDE */
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#define PC104_IO_BASE 0xb8000000
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#define PC104_MEM_BASE 0xba000000
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#define SMC_IO_SIZE 0x100
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#define CF_OFFSET 0x1f0
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#define IDE_OFFSET 0x170
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#endif /* __MACH_SH2007_H */
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