49 lines
1.2 KiB
C
49 lines
1.2 KiB
C
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/*
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* Copyright 2004-2009 Analog Devices Inc.
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* Tony Kou (tonyko@lineo.ca)
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _BLACKFIN_BARRIER_H
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#define _BLACKFIN_BARRIER_H
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#include <asm/cache.h>
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#define nop() __asm__ __volatile__ ("nop;\n\t" : : )
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/*
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* Force strict CPU ordering.
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*/
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#ifdef CONFIG_SMP
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#ifdef __ARCH_SYNC_CORE_DCACHE
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/* Force Core data cache coherence */
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# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
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# define rmb() do { barrier(); smp_check_barrier(); } while (0)
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# define wmb() do { barrier(); smp_mark_barrier(); } while (0)
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# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
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#else
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# define mb() barrier()
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# define rmb() barrier()
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# define wmb() barrier()
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# define read_barrier_depends() do { } while (0)
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#endif
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#else /* !CONFIG_SMP */
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define read_barrier_depends() do { } while (0)
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#endif /* !CONFIG_SMP */
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define smp_read_barrier_depends() read_barrier_depends()
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#endif /* _BLACKFIN_BARRIER_H */
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