445 lines
11 KiB
C
445 lines
11 KiB
C
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/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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#include <mach/subsystem_restart.h>
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#include <mach/scm.h>
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#include <mach/ramdump.h>
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#include "peripheral-loader.h"
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#include "scm-pas.h"
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#define QDSP6SS_RST_EVB 0x0000
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#define QDSP6SS_STRAP_TCM 0x001C
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#define QDSP6SS_STRAP_AHB 0x0020
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#define LCC_Q6_FUNC 0x001C
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#define LV_EN BIT(27)
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#define STOP_CORE BIT(26)
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#define CLAMP_IO BIT(25)
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#define Q6SS_PRIV_ARES BIT(24)
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#define Q6SS_SS_ARES BIT(23)
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#define Q6SS_ISDB_ARES BIT(22)
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#define Q6SS_ETM_ARES BIT(21)
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#define Q6_JTAG_CRC_EN BIT(20)
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#define Q6_JTAG_INV_EN BIT(19)
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#define Q6_JTAG_CXC_EN BIT(18)
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#define Q6_PXO_CRC_EN BIT(17)
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#define Q6_PXO_INV_EN BIT(16)
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#define Q6_PXO_CXC_EN BIT(15)
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#define Q6_PXO_SLEEP_EN BIT(14)
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#define Q6_SLP_CRC_EN BIT(13)
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#define Q6_SLP_INV_EN BIT(12)
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#define Q6_SLP_CXC_EN BIT(11)
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#define CORE_ARES BIT(10)
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#define CORE_L1_MEM_CORE_EN BIT(9)
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#define CORE_TCM_MEM_CORE_EN BIT(8)
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#define CORE_TCM_MEM_PERPH_EN BIT(7)
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#define CORE_GFM4_CLK_EN BIT(2)
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#define CORE_GFM4_RES BIT(1)
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#define RAMP_PLL_SRC_SEL BIT(0)
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#define Q6_STRAP_AHB_UPPER (0x290 << 12)
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#define Q6_STRAP_AHB_LOWER 0x280
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#define Q6_STRAP_TCM_BASE (0x28C << 15)
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#define Q6_STRAP_TCM_CONFIG 0x28B
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#define SCM_Q6_NMI_CMD 0x1
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/**
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* struct q6v3_data - LPASS driver data
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* @base: register base
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* @cbase: clock base
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* @wk_base: wakeup register base
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* @wd_base: watchdog register base
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* @irq: watchdog irq
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* @pil: peripheral handle
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* @subsys: subsystem restart handle
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* @subsys_desc: subsystem restart descriptor
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* @fatal_wrk: fatal error workqueue
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* @pll: pll clock handle
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* @ramdump_dev: ramdump device
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*/
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struct q6v3_data {
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void __iomem *base;
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void __iomem *cbase;
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void __iomem *wk_base;
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void __iomem *wd_base;
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int irq;
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struct pil_desc pil_desc;
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struct subsys_device *subsys;
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struct subsys_desc subsys_desc;
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struct work_struct fatal_wrk;
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struct clk *pll;
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struct ramdump_device *ramdump_dev;
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};
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static void pil_q6v3_remove_proxy_votes(struct pil_desc *pil)
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{
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struct q6v3_data *drv = dev_get_drvdata(pil->dev);
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clk_disable_unprepare(drv->pll);
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}
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static int pil_q6v3_make_proxy_votes(struct pil_desc *pil)
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{
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int ret;
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struct q6v3_data *drv = dev_get_drvdata(pil->dev);
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ret = clk_prepare_enable(drv->pll);
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if (ret) {
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dev_err(pil->dev, "Failed to enable PLL\n");
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return ret;
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}
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return 0;
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}
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static int pil_q6v3_reset(struct pil_desc *pil)
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{
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u32 reg;
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struct q6v3_data *drv = dev_get_drvdata(pil->dev);
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phys_addr_t start_addr = pil_get_entry_addr(pil);
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/* Put Q6 into reset */
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reg = readl_relaxed(drv->cbase + LCC_Q6_FUNC);
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reg |= Q6SS_SS_ARES | Q6SS_ISDB_ARES | Q6SS_ETM_ARES | STOP_CORE |
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CORE_ARES;
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reg &= ~CORE_GFM4_CLK_EN;
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writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
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/* Wait 8 AHB cycles for Q6 to be fully reset (AHB = 1.5Mhz) */
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usleep_range(20, 30);
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/* Turn on Q6 memory */
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reg |= CORE_GFM4_CLK_EN | CORE_L1_MEM_CORE_EN | CORE_TCM_MEM_CORE_EN |
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CORE_TCM_MEM_PERPH_EN;
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writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
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/* Turn on Q6 core clocks and take core out of reset */
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reg &= ~(CLAMP_IO | Q6SS_SS_ARES | Q6SS_ISDB_ARES | Q6SS_ETM_ARES |
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CORE_ARES);
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writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
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/* Wait for clocks to be enabled */
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mb();
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/* Program boot address */
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writel_relaxed((start_addr >> 12) & 0xFFFFF,
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drv->base + QDSP6SS_RST_EVB);
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writel_relaxed(Q6_STRAP_TCM_CONFIG | Q6_STRAP_TCM_BASE,
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drv->base + QDSP6SS_STRAP_TCM);
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writel_relaxed(Q6_STRAP_AHB_UPPER | Q6_STRAP_AHB_LOWER,
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drv->base + QDSP6SS_STRAP_AHB);
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/* Wait for addresses to be programmed before starting Q6 */
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mb();
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/* Start Q6 instruction execution */
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reg &= ~STOP_CORE;
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writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
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return 0;
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}
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static int pil_q6v3_shutdown(struct pil_desc *pil)
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{
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u32 reg;
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struct q6v3_data *drv = dev_get_drvdata(pil->dev);
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/* Put Q6 into reset */
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reg = readl_relaxed(drv->cbase + LCC_Q6_FUNC);
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reg |= Q6SS_SS_ARES | Q6SS_ISDB_ARES | Q6SS_ETM_ARES | STOP_CORE |
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CORE_ARES;
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reg &= ~CORE_GFM4_CLK_EN;
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writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
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/* Wait 8 AHB cycles for Q6 to be fully reset (AHB = 1.5Mhz) */
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usleep_range(20, 30);
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/* Turn off Q6 memory */
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reg &= ~(CORE_L1_MEM_CORE_EN | CORE_TCM_MEM_CORE_EN |
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CORE_TCM_MEM_PERPH_EN);
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writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
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reg |= CLAMP_IO;
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writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
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return 0;
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}
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static struct pil_reset_ops pil_q6v3_ops = {
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.auth_and_reset = pil_q6v3_reset,
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.shutdown = pil_q6v3_shutdown,
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.proxy_vote = pil_q6v3_make_proxy_votes,
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.proxy_unvote = pil_q6v3_remove_proxy_votes,
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};
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static int pil_q6v3_init_image_trusted(struct pil_desc *pil,
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const u8 *metadata, size_t size)
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{
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return pas_init_image(PAS_Q6, metadata, size);
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}
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static int pil_q6v3_reset_trusted(struct pil_desc *pil)
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{
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return pas_auth_and_reset(PAS_Q6);
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}
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static int pil_q6v3_shutdown_trusted(struct pil_desc *pil)
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{
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return pas_shutdown(PAS_Q6);
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}
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static struct pil_reset_ops pil_q6v3_ops_trusted = {
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.init_image = pil_q6v3_init_image_trusted,
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.auth_and_reset = pil_q6v3_reset_trusted,
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.shutdown = pil_q6v3_shutdown_trusted,
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.proxy_vote = pil_q6v3_make_proxy_votes,
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.proxy_unvote = pil_q6v3_remove_proxy_votes,
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};
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static void q6_fatal_fn(struct work_struct *work)
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{
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struct q6v3_data *drv = container_of(work, struct q6v3_data, fatal_wrk);
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pr_err("Watchdog bite received from Q6!\n");
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subsystem_restart_dev(drv->subsys);
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enable_irq(drv->irq);
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}
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static void send_q6_nmi(struct q6v3_data *drv)
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{
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/* Send NMI to QDSP6 via an SCM call. */
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scm_call_atomic1(SCM_SVC_UTIL, SCM_Q6_NMI_CMD, 0x1);
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/* Wakeup the Q6 */
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writel_relaxed(0x2000, drv->wk_base + 0x1c);
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/* Q6 requires atleast 100ms to dump caches etc.*/
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mdelay(100);
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pr_info("Q6 NMI was sent.\n");
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}
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static int lpass_q6_start(const struct subsys_desc *subsys)
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{
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struct q6v3_data *drv;
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drv = container_of(subsys, struct q6v3_data, subsys_desc);
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return pil_boot(&drv->pil_desc);
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}
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static void lpass_q6_stop(const struct subsys_desc *subsys)
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{
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struct q6v3_data *drv;
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drv = container_of(subsys, struct q6v3_data, subsys_desc);
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pil_shutdown(&drv->pil_desc);
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}
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static int lpass_q6_shutdown(const struct subsys_desc *subsys)
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{
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struct q6v3_data *drv;
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drv = container_of(subsys, struct q6v3_data, subsys_desc);
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send_q6_nmi(drv);
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writel_relaxed(0x0, drv->wd_base + 0x24);
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mb();
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pil_shutdown(&drv->pil_desc);
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disable_irq_nosync(drv->irq);
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return 0;
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}
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static int lpass_q6_powerup(const struct subsys_desc *subsys)
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{
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struct q6v3_data *drv;
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int ret;
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drv = container_of(subsys, struct q6v3_data, subsys_desc);
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ret = pil_boot(&drv->pil_desc);
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enable_irq(drv->irq);
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return ret;
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}
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static int lpass_q6_ramdump(int enable, const struct subsys_desc *subsys)
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{
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struct q6v3_data *drv;
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drv = container_of(subsys, struct q6v3_data, subsys_desc);
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if (!enable)
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return 0;
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return pil_do_ramdump(&drv->pil_desc, drv->ramdump_dev);
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}
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static void lpass_q6_crash_shutdown(const struct subsys_desc *subsys)
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{
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struct q6v3_data *drv;
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drv = container_of(subsys, struct q6v3_data, subsys_desc);
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send_q6_nmi(drv);
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}
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static irqreturn_t lpass_wdog_bite_irq(int irq, void *dev_id)
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{
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int ret;
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struct q6v3_data *drv = dev_id;
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ret = schedule_work(&drv->fatal_wrk);
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disable_irq_nosync(drv->irq);
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return IRQ_HANDLED;
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}
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static int __devinit pil_q6v3_driver_probe(struct platform_device *pdev)
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{
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struct q6v3_data *drv;
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struct resource *res;
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struct pil_desc *desc;
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int ret;
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drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
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if (!drv)
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return -ENOMEM;
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platform_set_drvdata(pdev, drv);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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drv->base = devm_request_and_ioremap(&pdev->dev, res);
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if (!drv->base)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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drv->wk_base = devm_request_and_ioremap(&pdev->dev, res);
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if (!drv->wk_base)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
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drv->wd_base = devm_request_and_ioremap(&pdev->dev, res);
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if (!drv->wd_base)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
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if (!res)
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return -EINVAL;
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drv->cbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
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if (!drv->cbase)
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return -ENOMEM;
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drv->irq = platform_get_irq(pdev, 0);
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if (drv->irq < 0)
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return drv->irq;
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|
|
|
||
|
|
drv->pll = devm_clk_get(&pdev->dev, "pll4");
|
||
|
|
if (IS_ERR(drv->pll))
|
||
|
|
return PTR_ERR(drv->pll);
|
||
|
|
|
||
|
|
desc = &drv->pil_desc;
|
||
|
|
desc->name = "q6";
|
||
|
|
desc->dev = &pdev->dev;
|
||
|
|
desc->owner = THIS_MODULE;
|
||
|
|
desc->proxy_timeout = 10000;
|
||
|
|
|
||
|
|
if (pas_supported(PAS_Q6) > 0) {
|
||
|
|
desc->ops = &pil_q6v3_ops_trusted;
|
||
|
|
dev_info(&pdev->dev, "using secure boot\n");
|
||
|
|
} else {
|
||
|
|
desc->ops = &pil_q6v3_ops;
|
||
|
|
dev_info(&pdev->dev, "using non-secure boot\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = pil_desc_init(desc);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
drv->subsys_desc.name = "adsp";
|
||
|
|
drv->subsys_desc.dev = &pdev->dev;
|
||
|
|
drv->subsys_desc.owner = THIS_MODULE;
|
||
|
|
drv->subsys_desc.start = lpass_q6_start;
|
||
|
|
drv->subsys_desc.stop = lpass_q6_stop;
|
||
|
|
drv->subsys_desc.shutdown = lpass_q6_shutdown;
|
||
|
|
drv->subsys_desc.powerup = lpass_q6_powerup;
|
||
|
|
drv->subsys_desc.ramdump = lpass_q6_ramdump;
|
||
|
|
drv->subsys_desc.crash_shutdown = lpass_q6_crash_shutdown;
|
||
|
|
|
||
|
|
INIT_WORK(&drv->fatal_wrk, q6_fatal_fn);
|
||
|
|
|
||
|
|
drv->ramdump_dev = create_ramdump_device("lpass", &pdev->dev);
|
||
|
|
if (!drv->ramdump_dev) {
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto err_ramdump;
|
||
|
|
}
|
||
|
|
|
||
|
|
drv->subsys = subsys_register(&drv->subsys_desc);
|
||
|
|
if (IS_ERR(drv->subsys)) {
|
||
|
|
ret = PTR_ERR(drv->subsys);
|
||
|
|
goto err_subsys;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = devm_request_irq(&pdev->dev, drv->irq, lpass_wdog_bite_irq,
|
||
|
|
IRQF_TRIGGER_RISING, "lpass_wdog", drv);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(&pdev->dev, "Unable to request wdog irq.\n");
|
||
|
|
goto err_irq;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
err_irq:
|
||
|
|
subsys_unregister(drv->subsys);
|
||
|
|
err_subsys:
|
||
|
|
destroy_ramdump_device(drv->ramdump_dev);
|
||
|
|
err_ramdump:
|
||
|
|
pil_desc_release(desc);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __devexit pil_q6v3_driver_exit(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct q6v3_data *drv = platform_get_drvdata(pdev);
|
||
|
|
subsys_unregister(drv->subsys);
|
||
|
|
destroy_ramdump_device(drv->ramdump_dev);
|
||
|
|
pil_desc_release(&drv->pil_desc);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver pil_q6v3_driver = {
|
||
|
|
.probe = pil_q6v3_driver_probe,
|
||
|
|
.remove = __devexit_p(pil_q6v3_driver_exit),
|
||
|
|
.driver = {
|
||
|
|
.name = "pil_qdsp6v3",
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init pil_q6v3_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&pil_q6v3_driver);
|
||
|
|
}
|
||
|
|
module_init(pil_q6v3_init);
|
||
|
|
|
||
|
|
static void __exit pil_q6v3_exit(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&pil_q6v3_driver);
|
||
|
|
}
|
||
|
|
module_exit(pil_q6v3_exit);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Support for booting QDSP6v3 (Hexagon) processors");
|
||
|
|
MODULE_LICENSE("GPL v2");
|