184 lines
5.4 KiB
C
184 lines
5.4 KiB
C
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/*
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* Copyright (c) 2011, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_8660_H
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#define __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_8660_H
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#define RPM_VREG_PIN_CTRL_PM8058_A0 0x01
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#define RPM_VREG_PIN_CTRL_PM8058_A1 0x02
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#define RPM_VREG_PIN_CTRL_PM8058_D0 0x04
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#define RPM_VREG_PIN_CTRL_PM8058_D1 0x08
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#define RPM_VREG_PIN_CTRL_PM8901_A0 0x01
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#define RPM_VREG_PIN_CTRL_PM8901_A1 0x02
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#define RPM_VREG_PIN_CTRL_PM8901_D0 0x04
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#define RPM_VREG_PIN_CTRL_PM8901_D1 0x08
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/**
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* enum rpm_vreg_pin_fn_8660 - RPM regulator pin function choices
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* %RPM_VREG_PIN_FN_8660_ENABLE: pin control switches between disable and
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* enable
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* %RPM_VREG_PIN_FN_8660_MODE: pin control switches between LPM and HPM
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* %RPM_VREG_PIN_FN_8660_SLEEP_B: regulator is forced into LPM when
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* sleep_b signal is asserted
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* %RPM_VREG_PIN_FN_8660_NONE: do not use pin control for the regulator
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* and do not allow another master to
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* request pin control
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*
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* The pin function specified in platform data corresponds to the active state
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* pin function value. Pin function will be NONE until a consumer requests
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* pin control to be enabled.
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*/
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enum rpm_vreg_pin_fn_8660 {
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RPM_VREG_PIN_FN_8660_ENABLE = 0,
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RPM_VREG_PIN_FN_8660_MODE,
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RPM_VREG_PIN_FN_8660_SLEEP_B,
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RPM_VREG_PIN_FN_8660_NONE,
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};
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/**
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* enum rpm_vreg_force_mode_8660 - RPM regulator force mode choices
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* %RPM_VREG_FORCE_MODE_8660_PIN_CTRL: allow pin control usage
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* %RPM_VREG_FORCE_MODE_8660_NONE: do not force any mode
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* %RPM_VREG_FORCE_MODE_8660_LPM: force into low power mode
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* %RPM_VREG_FORCE_MODE_8660_HPM: force into high power mode
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*
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* Force mode is used to override aggregation with other masters and to set
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* special operating modes.
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*/
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enum rpm_vreg_force_mode_8660 {
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RPM_VREG_FORCE_MODE_8660_PIN_CTRL = 0,
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RPM_VREG_FORCE_MODE_8660_NONE = 0,
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RPM_VREG_FORCE_MODE_8660_LPM,
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RPM_VREG_FORCE_MODE_8660_HPM,
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};
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enum rpm_vreg_id_8660 {
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RPM_VREG_ID_PM8058_L0,
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RPM_VREG_ID_PM8058_L1,
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RPM_VREG_ID_PM8058_L2,
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RPM_VREG_ID_PM8058_L3,
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RPM_VREG_ID_PM8058_L4,
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RPM_VREG_ID_PM8058_L5,
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RPM_VREG_ID_PM8058_L6,
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RPM_VREG_ID_PM8058_L7,
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RPM_VREG_ID_PM8058_L8,
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RPM_VREG_ID_PM8058_L9,
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RPM_VREG_ID_PM8058_L10,
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RPM_VREG_ID_PM8058_L11,
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RPM_VREG_ID_PM8058_L12,
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RPM_VREG_ID_PM8058_L13,
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RPM_VREG_ID_PM8058_L14,
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RPM_VREG_ID_PM8058_L15,
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RPM_VREG_ID_PM8058_L16,
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RPM_VREG_ID_PM8058_L17,
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RPM_VREG_ID_PM8058_L18,
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RPM_VREG_ID_PM8058_L19,
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RPM_VREG_ID_PM8058_L20,
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RPM_VREG_ID_PM8058_L21,
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RPM_VREG_ID_PM8058_L22,
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RPM_VREG_ID_PM8058_L23,
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RPM_VREG_ID_PM8058_L24,
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RPM_VREG_ID_PM8058_L25,
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RPM_VREG_ID_PM8058_S0,
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RPM_VREG_ID_PM8058_S1,
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RPM_VREG_ID_PM8058_S2,
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RPM_VREG_ID_PM8058_S3,
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RPM_VREG_ID_PM8058_S4,
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RPM_VREG_ID_PM8058_LVS0,
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RPM_VREG_ID_PM8058_LVS1,
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RPM_VREG_ID_PM8058_NCP,
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RPM_VREG_ID_PM8901_L0,
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RPM_VREG_ID_PM8901_L1,
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RPM_VREG_ID_PM8901_L2,
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RPM_VREG_ID_PM8901_L3,
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RPM_VREG_ID_PM8901_L4,
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RPM_VREG_ID_PM8901_L5,
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RPM_VREG_ID_PM8901_L6,
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RPM_VREG_ID_PM8901_S0,
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RPM_VREG_ID_PM8901_S1,
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RPM_VREG_ID_PM8901_S2,
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RPM_VREG_ID_PM8901_S3,
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RPM_VREG_ID_PM8901_S4,
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RPM_VREG_ID_PM8901_LVS0,
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RPM_VREG_ID_PM8901_LVS1,
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RPM_VREG_ID_PM8901_LVS2,
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RPM_VREG_ID_PM8901_LVS3,
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RPM_VREG_ID_PM8901_MVS0,
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RPM_VREG_ID_8660_MAX_REAL = RPM_VREG_ID_PM8901_MVS0,
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/* The following are IDs for regulator devices to enable pin control. */
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RPM_VREG_ID_PM8058_L0_PC,
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RPM_VREG_ID_PM8058_L1_PC,
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RPM_VREG_ID_PM8058_L2_PC,
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RPM_VREG_ID_PM8058_L3_PC,
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RPM_VREG_ID_PM8058_L4_PC,
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RPM_VREG_ID_PM8058_L5_PC,
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RPM_VREG_ID_PM8058_L6_PC,
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RPM_VREG_ID_PM8058_L7_PC,
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RPM_VREG_ID_PM8058_L8_PC,
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RPM_VREG_ID_PM8058_L9_PC,
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RPM_VREG_ID_PM8058_L10_PC,
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RPM_VREG_ID_PM8058_L11_PC,
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RPM_VREG_ID_PM8058_L12_PC,
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RPM_VREG_ID_PM8058_L13_PC,
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RPM_VREG_ID_PM8058_L14_PC,
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RPM_VREG_ID_PM8058_L15_PC,
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RPM_VREG_ID_PM8058_L16_PC,
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RPM_VREG_ID_PM8058_L17_PC,
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RPM_VREG_ID_PM8058_L18_PC,
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RPM_VREG_ID_PM8058_L19_PC,
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RPM_VREG_ID_PM8058_L20_PC,
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RPM_VREG_ID_PM8058_L21_PC,
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RPM_VREG_ID_PM8058_L22_PC,
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RPM_VREG_ID_PM8058_L23_PC,
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RPM_VREG_ID_PM8058_L24_PC,
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RPM_VREG_ID_PM8058_L25_PC,
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RPM_VREG_ID_PM8058_S0_PC,
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RPM_VREG_ID_PM8058_S1_PC,
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RPM_VREG_ID_PM8058_S2_PC,
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RPM_VREG_ID_PM8058_S3_PC,
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RPM_VREG_ID_PM8058_S4_PC,
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RPM_VREG_ID_PM8058_LVS0_PC,
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RPM_VREG_ID_PM8058_LVS1_PC,
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RPM_VREG_ID_PM8901_L0_PC,
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RPM_VREG_ID_PM8901_L1_PC,
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RPM_VREG_ID_PM8901_L2_PC,
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RPM_VREG_ID_PM8901_L3_PC,
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RPM_VREG_ID_PM8901_L4_PC,
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RPM_VREG_ID_PM8901_L5_PC,
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RPM_VREG_ID_PM8901_L6_PC,
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RPM_VREG_ID_PM8901_S0_PC,
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RPM_VREG_ID_PM8901_S1_PC,
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RPM_VREG_ID_PM8901_S2_PC,
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RPM_VREG_ID_PM8901_S3_PC,
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RPM_VREG_ID_PM8901_S4_PC,
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RPM_VREG_ID_PM8901_LVS0_PC,
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RPM_VREG_ID_PM8901_LVS1_PC,
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RPM_VREG_ID_PM8901_LVS2_PC,
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RPM_VREG_ID_PM8901_LVS3_PC,
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RPM_VREG_ID_PM8901_MVS0_PC,
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RPM_VREG_ID_8660_MAX = RPM_VREG_ID_PM8901_MVS0_PC,
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};
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/* Minimum high power mode loads in uA. */
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#define RPM_VREG_8660_LDO_50_HPM_MIN_LOAD 5000
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#define RPM_VREG_8660_LDO_150_HPM_MIN_LOAD 10000
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#define RPM_VREG_8660_LDO_300_HPM_MIN_LOAD 10000
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#define RPM_VREG_8660_SMPS_HPM_MIN_LOAD 50000
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#define RPM_VREG_8660_FTSMPS_HPM_MIN_LOAD 100000
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#endif
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