95 lines
3.0 KiB
C
95 lines
3.0 KiB
C
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/*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2008-2010, The Linux Foundation. All rights reserved.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* The MSM peripherals are spread all over across 768MB of physical
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* space, which makes just having a simple IO_ADDRESS macro to slide
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* them into the right virtual location rough. Instead, we will
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* provide a master phys->virt mapping for peripherals here.
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*
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*/
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#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H
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#define __ASM_ARCH_MSM_IOMAP_8X50_H
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/* Physical base address and size of peripherals.
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* Ordered by the virtual base addresses they will be mapped at.
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*
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* MSM_VIC_BASE must be an value that can be loaded via a "mov"
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* instruction, otherwise entry-macro.S will not compile.
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*
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* If you add or remove entries here, you'll want to edit the
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* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
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* changes.
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*
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*/
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#define MSM_VIC_BASE IOMEM(0xFA000000)
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#define MSM_VIC_PHYS 0xAC000000
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#define MSM_VIC_SIZE SZ_4K
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#define MSM_CSR_BASE IOMEM(0xFA001000)
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#define MSM_CSR_PHYS 0xAC100000
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#define MSM_CSR_SIZE SZ_4K
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#define MSM_TMR_PHYS MSM_CSR_PHYS
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#define MSM_TMR_BASE MSM_CSR_BASE
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#define MSM_TMR_SIZE SZ_4K
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#define MSM_GPIO1_BASE IOMEM(0xFA003000)
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#define MSM_GPIO1_PHYS 0xA9000000
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#define MSM_GPIO1_SIZE SZ_4K
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#define MSM_GPIO2_BASE IOMEM(0xFA004000)
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#define MSM_GPIO2_PHYS 0xA9100000
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#define MSM_GPIO2_SIZE SZ_4K
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#define MSM_CLK_CTL_BASE IOMEM(0xFA005000)
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#define MSM_CLK_CTL_PHYS 0xA8600000
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#define MSM_CLK_CTL_SIZE SZ_4K
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#define MSM_SIRC_BASE IOMEM(0xFB006000)
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#define MSM_SIRC_PHYS 0xAC200000
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#define MSM_SIRC_SIZE SZ_4K
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#define MSM_SCPLL_BASE IOMEM(0xFB007000)
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#define MSM_SCPLL_PHYS 0xA8800000
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#define MSM_SCPLL_SIZE SZ_4K
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#define MSM_TCSR_BASE IOMEM(0xFB008000)
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#define MSM_TCSR_PHYS 0xA8700000
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#define MSM_TCSR_SIZE SZ_4K
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#define MSM_SHARED_RAM_BASE IOMEM(0xFA100000)
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#define MSM_SHARED_RAM_SIZE SZ_1M
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#define MSM_UART1_PHYS 0xA9A00000
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#define MSM_UART1_SIZE SZ_4K
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#define MSM_UART2_PHYS 0xA9B00000
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#define MSM_UART2_SIZE SZ_4K
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#define MSM_UART3_PHYS 0xA9C00000
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#define MSM_UART3_SIZE SZ_4K
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#define MSM_MDC_BASE IOMEM(0xFA200000)
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#define MSM_MDC_PHYS 0xAA500000
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#define MSM_MDC_SIZE SZ_1M
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#define MSM_AD5_BASE IOMEM(0xFA300000)
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#define MSM_AD5_PHYS 0xAC000000
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#define MSM_AD5_SIZE (SZ_1M*13)
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#endif
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