396 lines
15 KiB
C
396 lines
15 KiB
C
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/* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <asm/processor.h>
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#include <mach/msm_iomap.h>
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#include "clock-dss-8960.h"
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/* HDMI PLL macros */
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#define HDMI_PHY_PLL_REFCLK_CFG (MSM_HDMI_BASE + 0x00000500)
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#define HDMI_PHY_PLL_CHRG_PUMP_CFG (MSM_HDMI_BASE + 0x00000504)
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#define HDMI_PHY_PLL_LOOP_FLT_CFG0 (MSM_HDMI_BASE + 0x00000508)
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#define HDMI_PHY_PLL_LOOP_FLT_CFG1 (MSM_HDMI_BASE + 0x0000050c)
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#define HDMI_PHY_PLL_IDAC_ADJ_CFG (MSM_HDMI_BASE + 0x00000510)
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#define HDMI_PHY_PLL_I_VI_KVCO_CFG (MSM_HDMI_BASE + 0x00000514)
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#define HDMI_PHY_PLL_PWRDN_B (MSM_HDMI_BASE + 0x00000518)
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#define HDMI_PHY_PLL_SDM_CFG0 (MSM_HDMI_BASE + 0x0000051c)
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#define HDMI_PHY_PLL_SDM_CFG1 (MSM_HDMI_BASE + 0x00000520)
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#define HDMI_PHY_PLL_SDM_CFG2 (MSM_HDMI_BASE + 0x00000524)
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#define HDMI_PHY_PLL_SDM_CFG3 (MSM_HDMI_BASE + 0x00000528)
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#define HDMI_PHY_PLL_SDM_CFG4 (MSM_HDMI_BASE + 0x0000052c)
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#define HDMI_PHY_PLL_SSC_CFG0 (MSM_HDMI_BASE + 0x00000530)
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#define HDMI_PHY_PLL_SSC_CFG1 (MSM_HDMI_BASE + 0x00000534)
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#define HDMI_PHY_PLL_SSC_CFG2 (MSM_HDMI_BASE + 0x00000538)
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#define HDMI_PHY_PLL_SSC_CFG3 (MSM_HDMI_BASE + 0x0000053c)
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#define HDMI_PHY_PLL_LOCKDET_CFG0 (MSM_HDMI_BASE + 0x00000540)
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#define HDMI_PHY_PLL_LOCKDET_CFG1 (MSM_HDMI_BASE + 0x00000544)
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#define HDMI_PHY_PLL_LOCKDET_CFG2 (MSM_HDMI_BASE + 0x00000548)
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#define HDMI_PHY_PLL_VCOCAL_CFG0 (MSM_HDMI_BASE + 0x0000054c)
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#define HDMI_PHY_PLL_VCOCAL_CFG1 (MSM_HDMI_BASE + 0x00000550)
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#define HDMI_PHY_PLL_VCOCAL_CFG2 (MSM_HDMI_BASE + 0x00000554)
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#define HDMI_PHY_PLL_VCOCAL_CFG3 (MSM_HDMI_BASE + 0x00000558)
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#define HDMI_PHY_PLL_VCOCAL_CFG4 (MSM_HDMI_BASE + 0x0000055c)
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#define HDMI_PHY_PLL_VCOCAL_CFG5 (MSM_HDMI_BASE + 0x00000560)
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#define HDMI_PHY_PLL_VCOCAL_CFG6 (MSM_HDMI_BASE + 0x00000564)
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#define HDMI_PHY_PLL_VCOCAL_CFG7 (MSM_HDMI_BASE + 0x00000568)
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#define HDMI_PHY_PLL_DEBUG_SEL (MSM_HDMI_BASE + 0x0000056c)
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#define HDMI_PHY_PLL_MISC0 (MSM_HDMI_BASE + 0x00000570)
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#define HDMI_PHY_PLL_MISC1 (MSM_HDMI_BASE + 0x00000574)
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#define HDMI_PHY_PLL_MISC2 (MSM_HDMI_BASE + 0x00000578)
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#define HDMI_PHY_PLL_MISC3 (MSM_HDMI_BASE + 0x0000057c)
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#define HDMI_PHY_PLL_MISC4 (MSM_HDMI_BASE + 0x00000580)
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#define HDMI_PHY_PLL_MISC5 (MSM_HDMI_BASE + 0x00000584)
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#define HDMI_PHY_PLL_MISC6 (MSM_HDMI_BASE + 0x00000588)
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#define HDMI_PHY_PLL_DEBUG_BUS0 (MSM_HDMI_BASE + 0x0000058c)
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#define HDMI_PHY_PLL_DEBUG_BUS1 (MSM_HDMI_BASE + 0x00000590)
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#define HDMI_PHY_PLL_DEBUG_BUS2 (MSM_HDMI_BASE + 0x00000594)
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#define HDMI_PHY_PLL_STATUS0 (MSM_HDMI_BASE + 0x00000598)
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#define HDMI_PHY_PLL_STATUS1 (MSM_HDMI_BASE + 0x0000059c)
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#define HDMI_PHY_CTRL (MSM_HDMI_BASE + 0x000002D4)
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#define HDMI_PHY_REG_0 (MSM_HDMI_BASE + 0x00000400)
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#define HDMI_PHY_REG_1 (MSM_HDMI_BASE + 0x00000404)
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#define HDMI_PHY_REG_2 (MSM_HDMI_BASE + 0x00000408)
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#define HDMI_PHY_REG_3 (MSM_HDMI_BASE + 0x0000040c)
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#define HDMI_PHY_REG_4 (MSM_HDMI_BASE + 0x00000410)
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#define HDMI_PHY_REG_5 (MSM_HDMI_BASE + 0x00000414)
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#define HDMI_PHY_REG_6 (MSM_HDMI_BASE + 0x00000418)
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#define HDMI_PHY_REG_7 (MSM_HDMI_BASE + 0x0000041c)
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#define HDMI_PHY_REG_8 (MSM_HDMI_BASE + 0x00000420)
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#define HDMI_PHY_REG_9 (MSM_HDMI_BASE + 0x00000424)
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#define HDMI_PHY_REG_10 (MSM_HDMI_BASE + 0x00000428)
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#define HDMI_PHY_REG_11 (MSM_HDMI_BASE + 0x0000042c)
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#define HDMI_PHY_REG_12 (MSM_HDMI_BASE + 0x00000430)
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#define HDMI_PHY_REG_BIST_CFG (MSM_HDMI_BASE + 0x00000434)
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#define HDMI_PHY_DEBUG_BUS_SEL (MSM_HDMI_BASE + 0x00000438)
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#define HDMI_PHY_REG_MISC0 (MSM_HDMI_BASE + 0x0000043c)
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#define HDMI_PHY_REG_13 (MSM_HDMI_BASE + 0x00000440)
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#define HDMI_PHY_REG_14 (MSM_HDMI_BASE + 0x00000444)
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#define HDMI_PHY_REG_15 (MSM_HDMI_BASE + 0x00000448)
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#define AHB_EN_REG (MSM_MMSS_CLK_CTL_BASE + 0x0008)
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/* HDMI PHY/PLL bit field macros */
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#define SW_RESET BIT(2)
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#define SW_RESET_PLL BIT(0)
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#define PWRDN_B BIT(7)
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#define PLL_PWRDN_B BIT(3)
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#define PD_PLL BIT(1)
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static unsigned hdmi_pll_on;
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int hdmi_pll_enable(void)
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{
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unsigned int val;
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u32 ahb_en_reg, ahb_enabled;
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unsigned int timeout_count;
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int pll_lock_retry = 10;
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ahb_en_reg = readl_relaxed(AHB_EN_REG);
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ahb_enabled = ahb_en_reg & BIT(4);
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if (!ahb_enabled) {
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writel_relaxed(ahb_en_reg | BIT(4), AHB_EN_REG);
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/* Make sure iface clock is enabled before register access */
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mb();
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}
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/* Assert PLL S/W reset */
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writel_relaxed(0x8D, HDMI_PHY_PLL_LOCKDET_CFG2);
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writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
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writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
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/* Wait for a short time before de-asserting
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* to allow the hardware to complete its job.
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* This much of delay should be fine for hardware
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* to assert and de-assert.
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*/
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udelay(10);
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/* De-assert PLL S/W reset */
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writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
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val = readl_relaxed(HDMI_PHY_REG_12);
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val |= BIT(5);
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/* Assert PHY S/W reset */
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writel_relaxed(val, HDMI_PHY_REG_12);
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val &= ~BIT(5);
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/* Wait for a short time before de-asserting
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to allow the hardware to complete its job.
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This much of delay should be fine for hardware
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to assert and de-assert. */
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udelay(10);
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/* De-assert PHY S/W reset */
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writel_relaxed(val, HDMI_PHY_REG_12);
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writel_relaxed(0x3f, HDMI_PHY_REG_2);
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val = readl_relaxed(HDMI_PHY_REG_12);
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val |= PWRDN_B;
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writel_relaxed(val, HDMI_PHY_REG_12);
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/* Wait 10 us for enabling global power for PHY */
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mb();
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udelay(10);
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val = readl_relaxed(HDMI_PHY_PLL_PWRDN_B);
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val |= PLL_PWRDN_B;
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val &= ~PD_PLL;
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writel_relaxed(val, HDMI_PHY_PLL_PWRDN_B);
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writel_relaxed(0x80, HDMI_PHY_REG_2);
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timeout_count = 1000;
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while (!(readl_relaxed(HDMI_PHY_PLL_STATUS0) & BIT(0)) &&
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timeout_count && pll_lock_retry) {
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if (--timeout_count == 0) {
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/*
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* PLL has still not locked.
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* Do a software reset and try again
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* Assert PLL S/W reset first
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*/
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writel_relaxed(0x8D, HDMI_PHY_PLL_LOCKDET_CFG2);
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/* Wait for a short time before de-asserting
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* to allow the hardware to complete its job.
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* This much of delay should be fine for hardware
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* to assert and de-assert.
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*/
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udelay(10);
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writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
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/*
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* Wait for a short duration for the PLL calibration
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* before checking if the PLL gets locked
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*/
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udelay(350);
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timeout_count = 1000;
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pll_lock_retry--;
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}
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}
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if (!ahb_enabled)
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writel_relaxed(ahb_en_reg & ~BIT(4), AHB_EN_REG);
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if (!pll_lock_retry) {
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pr_err("%s: HDMI PLL not locked\n", __func__);
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hdmi_pll_disable();
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return -EAGAIN;
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}
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hdmi_pll_on = 1;
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return 0;
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}
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void hdmi_pll_disable(void)
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{
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unsigned int val;
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u32 ahb_en_reg, ahb_enabled;
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ahb_en_reg = readl_relaxed(AHB_EN_REG);
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ahb_enabled = ahb_en_reg & BIT(4);
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if (!ahb_enabled) {
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writel_relaxed(ahb_en_reg | BIT(4), AHB_EN_REG);
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mb();
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}
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val = readl_relaxed(HDMI_PHY_REG_12);
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val &= (~PWRDN_B);
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writel_relaxed(val, HDMI_PHY_REG_12);
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val = readl_relaxed(HDMI_PHY_PLL_PWRDN_B);
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val |= PD_PLL;
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val &= (~PLL_PWRDN_B);
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writel_relaxed(val, HDMI_PHY_PLL_PWRDN_B);
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/* Make sure HDMI PHY/PLL are powered down */
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mb();
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if (!ahb_enabled)
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writel_relaxed(ahb_en_reg & ~BIT(4), AHB_EN_REG);
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hdmi_pll_on = 0;
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}
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int hdmi_pll_set_rate(unsigned rate)
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{
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unsigned int set_power_dwn = 0;
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u32 ahb_en_reg = readl_relaxed(AHB_EN_REG);
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u32 ahb_enabled = ahb_en_reg & BIT(4);
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if (!ahb_enabled) {
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writel_relaxed(ahb_en_reg | BIT(4), AHB_EN_REG);
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/* Make sure iface clock is enabled before register access */
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mb();
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}
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if (hdmi_pll_on) {
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hdmi_pll_disable();
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set_power_dwn = 1;
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}
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switch (rate) {
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case 27030000:
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/* 480p60/480i60 case */
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writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
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writel_relaxed(0x38, HDMI_PHY_PLL_REFCLK_CFG);
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writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
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writel_relaxed(0x20, HDMI_PHY_PLL_LOOP_FLT_CFG0);
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writel_relaxed(0xFF, HDMI_PHY_PLL_LOOP_FLT_CFG1);
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writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG0);
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writel_relaxed(0x4E, HDMI_PHY_PLL_SDM_CFG1);
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writel_relaxed(0xD7, HDMI_PHY_PLL_SDM_CFG2);
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writel_relaxed(0x03, HDMI_PHY_PLL_SDM_CFG3);
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writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
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writel_relaxed(0x2A, HDMI_PHY_PLL_VCOCAL_CFG0);
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writel_relaxed(0x03, HDMI_PHY_PLL_VCOCAL_CFG1);
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writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
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writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
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writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
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writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
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writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
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writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
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break;
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case 25200000:
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/* 640x480p60 */
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writel_relaxed(0x32, HDMI_PHY_PLL_REFCLK_CFG);
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writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
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writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
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writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
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writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
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writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
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writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
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writel_relaxed(0x77, HDMI_PHY_PLL_SDM_CFG0);
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writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG1);
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writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG2);
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writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
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writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
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writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
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writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
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writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
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writel_relaxed(0x20, HDMI_PHY_PLL_SSC_CFG3);
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writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
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writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
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writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
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writel_relaxed(0xF4, HDMI_PHY_PLL_VCOCAL_CFG0);
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writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
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writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
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writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
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writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
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|
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
|
||
|
|
writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 27000000:
|
||
|
|
/* 576p50/576i50 case */
|
||
|
|
writel_relaxed(0x32, HDMI_PHY_PLL_REFCLK_CFG);
|
||
|
|
writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
|
||
|
|
writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
|
||
|
|
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
|
||
|
|
writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
|
||
|
|
writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
|
||
|
|
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
|
||
|
|
writel_relaxed(0x7B, HDMI_PHY_PLL_SDM_CFG0);
|
||
|
|
writel_relaxed(0x01, HDMI_PHY_PLL_SDM_CFG1);
|
||
|
|
writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG2);
|
||
|
|
writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
|
||
|
|
writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG3);
|
||
|
|
writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
|
||
|
|
writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
|
||
|
|
writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
|
||
|
|
writel_relaxed(0x2a, HDMI_PHY_PLL_VCOCAL_CFG0);
|
||
|
|
writel_relaxed(0x03, HDMI_PHY_PLL_VCOCAL_CFG1);
|
||
|
|
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
|
||
|
|
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
|
||
|
|
writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 74250000:
|
||
|
|
/* 720p60/720p50/1080i60/1080i50
|
||
|
|
* 1080p24/1080p30/1080p25 case
|
||
|
|
*/
|
||
|
|
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
|
||
|
|
writel_relaxed(0x12, HDMI_PHY_PLL_REFCLK_CFG);
|
||
|
|
writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
|
||
|
|
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
|
||
|
|
writel_relaxed(0x76, HDMI_PHY_PLL_SDM_CFG0);
|
||
|
|
writel_relaxed(0xE6, HDMI_PHY_PLL_VCOCAL_CFG0);
|
||
|
|
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
|
||
|
|
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 108000000:
|
||
|
|
writel_relaxed(0x08, HDMI_PHY_PLL_REFCLK_CFG);
|
||
|
|
writel_relaxed(0x21, HDMI_PHY_PLL_LOOP_FLT_CFG0);
|
||
|
|
writel_relaxed(0xF9, HDMI_PHY_PLL_LOOP_FLT_CFG1);
|
||
|
|
writel_relaxed(0x1C, HDMI_PHY_PLL_VCOCAL_CFG0);
|
||
|
|
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
|
||
|
|
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
|
||
|
|
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
|
||
|
|
writel_relaxed(0x49, HDMI_PHY_PLL_SDM_CFG0);
|
||
|
|
writel_relaxed(0x49, HDMI_PHY_PLL_SDM_CFG1);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG2);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG3);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 148500000:
|
||
|
|
/* 1080p60/1080p50 case */
|
||
|
|
writel_relaxed(0x2, HDMI_PHY_PLL_REFCLK_CFG);
|
||
|
|
writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
|
||
|
|
writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
|
||
|
|
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
|
||
|
|
writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
|
||
|
|
writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
|
||
|
|
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
|
||
|
|
writel_relaxed(0x76, HDMI_PHY_PLL_SDM_CFG0);
|
||
|
|
writel_relaxed(0x01, HDMI_PHY_PLL_SDM_CFG1);
|
||
|
|
writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG2);
|
||
|
|
writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
|
||
|
|
writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG3);
|
||
|
|
writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
|
||
|
|
writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
|
||
|
|
writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
|
||
|
|
writel_relaxed(0xe6, HDMI_PHY_PLL_VCOCAL_CFG0);
|
||
|
|
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
|
||
|
|
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
|
||
|
|
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
|
||
|
|
writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
|
||
|
|
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Make sure writes complete before disabling iface clock */
|
||
|
|
mb();
|
||
|
|
|
||
|
|
if (set_power_dwn)
|
||
|
|
hdmi_pll_enable();
|
||
|
|
|
||
|
|
if (!ahb_enabled)
|
||
|
|
writel_relaxed(ahb_en_reg & ~BIT(4), AHB_EN_REG);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|