138 lines
3.9 KiB
C
138 lines
3.9 KiB
C
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/*
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* <mach/asp.h> - DaVinci Audio Serial Port support
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*/
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#ifndef __ASM_ARCH_DAVINCI_ASP_H
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#define __ASM_ARCH_DAVINCI_ASP_H
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#include <mach/irqs.h>
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#include <mach/edma.h>
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/* Bases of dm644x and dm355 register banks */
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#define DAVINCI_ASP0_BASE 0x01E02000
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#define DAVINCI_ASP1_BASE 0x01E04000
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/* Bases of dm365 register banks */
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#define DAVINCI_DM365_ASP0_BASE 0x01D02000
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/* Bases of dm646x register banks */
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#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
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#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
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/* Bases of da850/da830 McASP0 register banks */
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#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
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/* Bases of da830 McASP1 register banks */
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#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
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/* EDMA channels of dm644x and dm355 */
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#define DAVINCI_DMA_ASP0_TX 2
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#define DAVINCI_DMA_ASP0_RX 3
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#define DAVINCI_DMA_ASP1_TX 8
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#define DAVINCI_DMA_ASP1_RX 9
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/* EDMA channels of dm646x */
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#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
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#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
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#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
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/* EDMA channels of da850/da830 McASP0 */
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#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
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#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
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/* EDMA channels of da830 McASP1 */
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#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
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#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
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/* Interrupts */
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#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
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#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
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#define DAVINCI_ASP1_RX_INT IRQ_MBRINT
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#define DAVINCI_ASP1_TX_INT IRQ_MBXINT
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struct snd_platform_data {
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u32 tx_dma_offset;
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u32 rx_dma_offset;
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enum dma_event_q asp_chan_q; /* event queue number for ASP channel */
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enum dma_event_q ram_chan_q; /* event queue number for RAM channel */
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unsigned int codec_fmt;
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/*
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* Allowing this is more efficient and eliminates left and right swaps
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* caused by underruns, but will swap the left and right channels
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* when compared to previous behavior.
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*/
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unsigned enable_channel_combine:1;
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unsigned sram_size_playback;
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unsigned sram_size_capture;
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/*
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* If McBSP peripheral gets the clock from an external pin,
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* there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
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* and MCBSP_CLKS.
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* Depending on different hardware connections it is possible
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* to use this setting to change the behaviour of McBSP
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* driver. The dm365_clk_input_pin enum is available for dm365
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*/
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int clk_input_pin;
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/*
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* This flag works when both clock and FS are outputs for the cpu
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* and makes clock more accurate (FS is not symmetrical and the
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* clock is very fast.
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* The clock becoming faster is named
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* i2s continuous serial clock (I2S_SCK) and it is an externally
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* visible bit clock.
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*
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* first line : WordSelect
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* second line : ContinuousSerialClock
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* third line: SerialData
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*
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* SYMMETRICAL APPROACH:
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* _______________________ LEFT
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* _| RIGHT |______________________|
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* _ _ _ _ _ _ _ _
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* _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
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* _ _ _ _ _ _ _ _
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* _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
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* \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
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*
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* ACCURATE CLOCK APPROACH:
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* ______________ LEFT
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* _| RIGHT |_______________________________|
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* _ _ _ _ _ _ _ _ _
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* _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
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* _ _ _ _ dummy cycles
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* _/ \_ ... _/ \_/ \_ ... _/ \__________________
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* \_/ \_/ \_/ \_/
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*
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*/
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bool i2s_accurate_sck;
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/* McASP specific fields */
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int tdm_slots;
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u8 op_mode;
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u8 num_serializer;
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u8 *serial_dir;
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u8 version;
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u8 txnumevt;
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u8 rxnumevt;
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};
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enum {
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MCASP_VERSION_1 = 0, /* DM646x */
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MCASP_VERSION_2, /* DA8xx/OMAPL1x */
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};
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enum dm365_clk_input_pin {
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MCBSP_CLKR = 0, /* DM365 */
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MCBSP_CLKS,
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};
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#define INACTIVE_MODE 0
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#define TX_MODE 1
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#define RX_MODE 2
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#define DAVINCI_MCASP_IIS_MODE 0
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#define DAVINCI_MCASP_DIT_MODE 1
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#endif /* __ASM_ARCH_DAVINCI_ASP_H */
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