350 lines
9.0 KiB
C
350 lines
9.0 KiB
C
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/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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*
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* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <reg.h>
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#include <dev/gpio.h>
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#include <platform/iomap.h>
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#define ACPU_CLK 0 /* Applications processor clock */
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#define ADM_CLK 1 /* Applications data mover clock */
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#define ADSP_CLK 2 /* ADSP clock */
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#define EBI1_CLK 3 /* External bus interface 1 clock */
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#define EBI2_CLK 4 /* External bus interface 2 clock */
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#define ECODEC_CLK 5 /* External CODEC clock */
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#define EMDH_CLK 6 /* External MDDI host clock */
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#define GP_CLK 7 /* General purpose clock */
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#define GRP_CLK 8 /* Graphics clock */
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#define I2C_CLK 9 /* I2C clock */
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#define ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
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#define ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
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#define IMEM_CLK 12 /* Internal graphics memory clock */
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#define MDC_CLK 13 /* MDDI client clock */
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#define MDP_CLK 14 /* Mobile display processor clock */
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#define PBUS_CLK 15 /* Peripheral bus clock */
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#define PCM_CLK 16 /* PCM clock */
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#define PMDH_CLK 17 /* Primary MDDI host clock */
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#define SDAC_CLK 18 /* Stereo DAC clock */
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#define SDC1_CLK 19 /* Secure Digital Card clocks */
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#define SDC1_PCLK 20
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#define SDC2_CLK 21
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#define SDC2_PCLK 22
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#define SDC3_CLK 23
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#define SDC3_PCLK 24
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#define SDC4_CLK 25
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#define SDC4_PCLK 26
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#define TSIF_CLK 27 /* Transport Stream Interface clocks */
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#define TSIF_REF_CLK 28
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#define TV_DAC_CLK 29 /* TV clocks */
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#define TV_ENC_CLK 30
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#define UART1_CLK 31 /* UART clocks */
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#define UART2_CLK 32
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#define UART3_CLK 33
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#define UART1DM_CLK 34
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#define UART2DM_CLK 35
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#define USB_HS_CLK 36 /* High speed USB core clock */
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#define USB_HS_PCLK 37 /* High speed USB pbus clock */
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#define USB_OTG_CLK 38 /* Full speed USB clock */
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#define VDC_CLK 39 /* Video controller clock */
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#define VFE_CLK 40 /* Camera / Video Front End clock */
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#define VFE_MDC_CLK 41 /* VFE MDDI client clock */
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/* qsd8k adds... */
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#define MDP_LCDC_PCLK_CLK 42
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#define MDP_LCDC_PAD_PCLK_CLK 43
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#define MDP_VSYNC_CLK 44
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#define P_USB_HS_CORE_CLK 53 /* High speed USB 1 core clock */
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/* msm7x30 adds... */
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#define PMDH_P_CLK 82
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#define MDP_P_CLK 86
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enum {
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PCOM_CMD_IDLE = 0x0,
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PCOM_CMD_DONE,
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PCOM_RESET_APPS,
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PCOM_RESET_CHIP,
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PCOM_CONFIG_NAND_MPU,
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PCOM_CONFIG_USB_CLKS,
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PCOM_GET_POWER_ON_STATUS,
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PCOM_GET_WAKE_UP_STATUS,
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PCOM_GET_BATT_LEVEL,
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PCOM_CHG_IS_CHARGING,
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PCOM_POWER_DOWN,
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PCOM_USB_PIN_CONFIG,
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PCOM_USB_PIN_SEL,
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PCOM_SET_RTC_ALARM,
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PCOM_NV_READ,
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PCOM_NV_WRITE,
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PCOM_GET_UUID_HIGH,
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PCOM_GET_UUID_LOW,
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PCOM_GET_HW_ENTROPY,
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PCOM_RPC_GPIO_TLMM_CONFIG_REMOTE,
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PCOM_CLKCTL_RPC_ENABLE,
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PCOM_CLKCTL_RPC_DISABLE,
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PCOM_CLKCTL_RPC_RESET,
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PCOM_CLKCTL_RPC_SET_FLAGS,
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PCOM_CLKCTL_RPC_SET_RATE,
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PCOM_CLKCTL_RPC_MIN_RATE,
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PCOM_CLKCTL_RPC_MAX_RATE,
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PCOM_CLKCTL_RPC_RATE,
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PCOM_CLKCTL_RPC_PLL_REQUEST,
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PCOM_CLKCTL_RPC_ENABLED,
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PCOM_VREG_SWITCH,
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PCOM_VREG_SET_LEVEL,
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PCOM_GPIO_TLMM_CONFIG_GROUP,
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PCOM_GPIO_TLMM_UNCONFIG_GROUP,
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PCOM_NV_READ_HIGH_BITS,
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PCOM_NV_WRITE_HIGH_BITS,
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PCOM_RPC_GPIO_TLMM_CONFIG_EX = 0x25,
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PCOM_NUM_CMDS,
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PCOM_KERNEL_SEC_BOOT = 0x7A,
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};
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enum {
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PCOM_INVALID_STATUS = 0x0,
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PCOM_READY,
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PCOM_CMD_RUNNING,
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PCOM_CMD_SUCCESS,
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PCOM_CMD_FAIL,
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};
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#ifndef PLATFORM_MSM7X30
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#define MSM_A2M_INT(n) (MSM_CSR_BASE + 0x400 + (n) * 4)
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#endif
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static inline void notify_other_proc_comm(void)
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{
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#ifndef PLATFORM_MSM7X30
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writel(1, MSM_A2M_INT(6));
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#else
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writel(1 << 6, (MSM_GCC_BASE + 0x8));
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#endif
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}
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#define APP_COMMAND (MSM_SHARED_BASE + 0x00)
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#define APP_STATUS (MSM_SHARED_BASE + 0x04)
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#define APP_DATA1 (MSM_SHARED_BASE + 0x08)
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#define APP_DATA2 (MSM_SHARED_BASE + 0x0C)
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#define MDM_COMMAND (MSM_SHARED_BASE + 0x10)
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#define MDM_STATUS (MSM_SHARED_BASE + 0x14)
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#define MDM_DATA1 (MSM_SHARED_BASE + 0x18)
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#define MDM_DATA2 (MSM_SHARED_BASE + 0x1C)
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int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2)
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{
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int ret = -1;
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unsigned status;
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// dprintf(INFO, "proc_comm(%d,%d,%d)\n",
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// cmd, data1 ? *data1 : 0, data2 ? *data2 : 0);
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while (readl(MDM_STATUS) != PCOM_READY) {
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/* XXX check for A9 reset */
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}
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if (data1)
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writel(*data1, APP_DATA1);
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if (data2)
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writel(*data2, APP_DATA2);
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/*
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* As per the specs write data, cmd, interrupt for
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* proc comm processing
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*/
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writel(cmd, APP_COMMAND);
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// dprintf(INFO, "proc_comm tx\n");
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notify_other_proc_comm();
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while (readl(APP_COMMAND) != PCOM_CMD_DONE) {
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/* XXX check for A9 reset */
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}
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status = readl(APP_STATUS);
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// dprintf(INFO, "proc_comm status %d\n", status);
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if (status != PCOM_CMD_FAIL) {
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if (data1)
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*data1 = readl(APP_DATA1);
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if (data2)
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*data2 = readl(APP_DATA2);
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ret = 0;
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/*
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* Write command idle to indicate non HLOS that
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* apps has finished reading the status & data
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* of proc comm command
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*/
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writel(PCOM_CMD_IDLE, APP_COMMAND);
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}
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return ret;
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}
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static int clock_enable(unsigned id)
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{
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return msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, 0);
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}
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static int clock_disable(unsigned id)
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{
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return msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, 0);
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}
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static int clock_set_rate(unsigned id, unsigned rate)
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{
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return msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
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}
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static int clock_get_rate(unsigned id)
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{
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if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, 0)) {
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return -1;
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} else {
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return (int)id;
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}
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}
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void usb_clock_init()
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{
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clock_enable(USB_HS_PCLK);
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clock_enable(USB_HS_CLK);
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clock_enable(P_USB_HS_CORE_CLK);
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}
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void lcdc_clock_init(unsigned rate)
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{
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clock_set_rate(MDP_LCDC_PCLK_CLK, rate);
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clock_enable(MDP_LCDC_PCLK_CLK);
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clock_enable(MDP_LCDC_PAD_PCLK_CLK);
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}
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void mdp_clock_init(unsigned rate)
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{
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clock_set_rate(MDP_CLK, rate);
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clock_enable(MDP_CLK);
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}
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void mdp_clock_disable(void)
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{
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if(!target_cont_splash_screen())
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clock_disable(MDP_CLK);
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}
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void lcdc_clock_disable(void)
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{
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clock_disable(MDP_LCDC_PAD_PCLK_CLK);
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clock_disable(MDP_LCDC_PCLK_CLK);
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}
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void uart3_clock_init(void)
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{
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clock_enable(UART3_CLK);
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clock_set_rate(UART3_CLK, 19200000 / 4);
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}
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void uart2_clock_init(void)
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{
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clock_enable(UART2_CLK);
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clock_set_rate(UART2_CLK, 19200000);
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}
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void uart1_clock_init(void)
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{
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clock_enable(UART1_CLK);
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clock_set_rate(UART1_CLK, 19200000 / 4);
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}
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void mddi_clock_init(unsigned num, unsigned rate)
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{
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unsigned clock_id;
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if (num == 0)
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clock_id = PMDH_CLK;
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else
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clock_id = EMDH_CLK;
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clock_enable(clock_id);
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clock_set_rate(clock_id, rate);
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#ifdef PLATFORM_MSM7X30
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clock_enable(PMDH_P_CLK);
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#endif
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}
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void reboot(unsigned reboot_reason)
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{
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msm_proc_comm(PCOM_RESET_CHIP, &reboot_reason, 0);
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for (;;) ;
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}
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int mmc_clock_enable_disable(unsigned id, unsigned enable)
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{
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if (enable) {
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return clock_enable(id); //Enable mmc clock rate
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} else {
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return clock_disable(id); //Disable mmc clock rate
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}
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}
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int mmc_clock_set_rate(unsigned id, unsigned rate)
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{
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return clock_set_rate(id, rate); //Set mmc clock rate
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}
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int mmc_clock_get_rate(unsigned id)
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{
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return clock_get_rate(id); //Get mmc clock rate
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}
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int gpio_tlmm_config(unsigned config, unsigned disable)
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{
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return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable);
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}
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int vreg_set_level(unsigned id, unsigned mv)
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{
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return msm_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv);
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}
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int vreg_enable(unsigned id)
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{
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int enable = 1;
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return msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
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}
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int vreg_disable(unsigned id)
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{
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int enable = 0;
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return msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
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}
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void set_tamper_flag(int tamper)
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{
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return msm_proc_comm(PCOM_KERNEL_SEC_BOOT, &tamper, 0);
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}
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