411 lines
12 KiB
C
411 lines
12 KiB
C
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/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <mdp4.h>
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#include <debug.h>
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#include <reg.h>
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#include <target/display.h>
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#include <platform/timer.h>
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#include <platform/iomap.h>
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#include <dev/lcdc.h>
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#include <dev/fbcon.h>
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#include <bits.h>
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#include <msm_panel.h>
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#include <mipi_dsi.h>
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#include <err.h>
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#include <clock.h>
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static int mdp_rev;
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void
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mdp_setup_dma_p_video_config(unsigned short pack_pattern,
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unsigned short img_width,
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unsigned short img_height,
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unsigned long input_img_addr,
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unsigned short img_width_full_size,
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unsigned char ystride)
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{
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dprintf(SPEW, "MDP4.2 Setup for DSI Video Mode\n");
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// ----- programming MDP_AXI_RDMASTER_CONFIG --------
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/* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's
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the only port connected */
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//TODO: Seems to still work without this
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writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
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writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
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writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
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/* Set up CMD_INTF_SEL, VIDEO_INTF_SEL, EXT_INTF_SEL, SEC_INTF_SEL, PRIM_INTF_SEL */
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writel(0x00000049, MDP_DISP_INTF_SEL);
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/* DMA P */
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writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
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/* RGB 888 */
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writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG);
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writel(0x0, MDP_DMA_P_OUT_XY);
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writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
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writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
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writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
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}
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int
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mdp_setup_dma_p_video_mode(unsigned short disp_width,
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unsigned short disp_height,
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unsigned short img_width,
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unsigned short img_height,
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unsigned short hsync_porch0_fp,
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unsigned short hsync_porch0_bp,
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unsigned short vsync_porch0_fp,
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unsigned short vsync_porch0_bp,
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unsigned short hsync_width,
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unsigned short vsync_width,
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unsigned long input_img_addr,
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unsigned short img_width_full_size,
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unsigned short pack_pattern, unsigned char ystride)
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{
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// unsigned long mdp_intr_status;
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int status = FAIL;
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unsigned long hsync_period;
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unsigned long vsync_period;
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unsigned long vsync_period_intmd;
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dprintf(SPEW, "MDP4.1 for DSI Video Mode\n");
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hsync_period = img_width + hsync_porch0_fp + hsync_porch0_bp + 1;
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vsync_period_intmd = img_height + vsync_porch0_fp + vsync_porch0_bp + 1;
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vsync_period = vsync_period_intmd * hsync_period;
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// ----- programming MDP_AXI_RDMASTER_CONFIG --------
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/* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's
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the only port connected */
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writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
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writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
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writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
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/* sets PRIM_INTF_SEL to 0x1 and SEC_INTF_SEL to 0x2 and DSI_VIDEO_INTF_SEL */
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writel(0x00000049, MDP_DISP_INTF_SEL);
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writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
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// ------------- programming MDP_DMA_P_CONFIG ---------------------
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writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
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writel(0x00000000, MDP_DMA_P_OUT_XY);
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writel(img_height << 16 | img_width, MDP_DMA_P_SIZE);
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writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
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writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE);
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writel(0x00ff0000, MDP_DMA_P_OP_MODE);
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writel(hsync_period << 16 | hsync_width, MDP_DSI_VIDEO_HSYNC_CTL);
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writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
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writel(vsync_width * hsync_period, MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
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writel((img_width + hsync_porch0_bp - 1) << 16 | hsync_porch0_bp,
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MDP_DSI_VIDEO_DISPLAY_HCTL);
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writel(vsync_porch0_bp * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START);
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writel((img_height + vsync_porch0_bp) * hsync_period,
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MDP_DSI_VIDEO_DISPLAY_V_END);
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writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
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writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
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writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
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// end of cmd mdp
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writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE
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status = PASS;
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return status;
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}
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int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
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struct fbcon_config *fb)
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{
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int ret = 0;
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unsigned long input_img_addr = MIPI_FB_ADDR;
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unsigned short image_wd = pinfo->xres;
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unsigned short image_ht = pinfo->yres;
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unsigned short pack_pattern = 0x12;
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unsigned char ystride = 3;
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writel(0x03ffffff, MDP_INTR_ENABLE);
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writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
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// ------------- programming MDP_DMA_P_CONFIG ---------------------
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writel(pack_pattern << 8 | 0x3f | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
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writel(0x00000000, MDP_DMA_P_OUT_XY);
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writel(image_ht << 16 | image_wd, MDP_DMA_P_SIZE);
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writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
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writel(image_wd * ystride, MDP_DMA_P_BUF_Y_STRIDE);
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writel(0x00000000, MDP_DMA_P_OP_MODE);
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writel(0x10, MDP_DSI_CMD_MODE_ID_MAP);
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writel(0x01, MDP_DSI_CMD_MODE_TRIGGER_EN);
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writel(0x0001a000, MDP_AXI_RDMASTER_CONFIG);
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writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
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writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
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writel(0x8a, MDP_DISP_INTF_SEL);
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return ret;
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}
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int
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mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
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unsigned short num_of_lanes)
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{
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int status = 0;
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unsigned long input_img_addr = MIPI_FB_ADDR;
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unsigned short image_wd = mipi_fb_cfg.width;
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unsigned short image_ht = mipi_fb_cfg.height;
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unsigned short pack_pattern = 0x12;
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unsigned char ystride = 3;
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writel(0x03ffffff, MDP_INTR_ENABLE);
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writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
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// ------------- programming MDP_DMA_P_CONFIG ---------------------
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writel(pack_pattern << 8 | 0x3f | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
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writel(0x00000000, MDP_DMA_P_OUT_XY);
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writel(image_ht << 16 | image_wd, MDP_DMA_P_SIZE);
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writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
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writel(image_wd * ystride, MDP_DMA_P_BUF_Y_STRIDE);
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writel(0x00000000, MDP_DMA_P_OP_MODE);
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writel(0x10, MDP_DSI_CMD_MODE_ID_MAP);
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writel(0x01, MDP_DSI_CMD_MODE_TRIGGER_EN);
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writel(0x0001a000, MDP_AXI_RDMASTER_CONFIG);
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writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
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writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
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writel(0x8a, MDP_DISP_INTF_SEL);
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return status;
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}
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void mdp_disable(void)
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{
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writel(0x00000000, MDP_DSI_VIDEO_EN);
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}
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void mdp_shutdown(void)
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{
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mdp_disable();
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mdelay(60);
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writel(0x00000000, MDP_INTR_ENABLE);
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writel(0x00000003, MDP_OVERLAYPROC0_CFG);
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}
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int mdp_dma_on(void)
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{
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int ret = 0;
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writel(0x00000001, MDP_DMA_P_START);
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return ret;
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}
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int mdp_dma_off(void)
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{
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int ret = 0;
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writel(0x00000000, MDP_DMA_P_START);
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return ret;
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}
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void mdp_start_dma(void)
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{
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writel(0x00000001, MDP_DMA_P_START);
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}
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int mdp_dsi_video_config(struct msm_panel_info *pinfo,
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struct fbcon_config *fb)
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{
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int ret = NO_ERROR;
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int hsync_period, vsync_period;
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int hsync_start_x, hsync_end_x;
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int display_hctl, display_vstart, display_vend;
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struct lcdc_panel_info *lcdc = NULL;
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unsigned mdp_rgb_size;
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if (pinfo == NULL)
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return ERR_INVALID_ARGS;
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lcdc = &(pinfo->lcdc);
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if (lcdc == NULL)
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return ERR_INVALID_ARGS;
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hsync_period = lcdc->h_pulse_width +
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lcdc->h_back_porch +
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pinfo->xres + lcdc->xres_pad + lcdc->h_front_porch;
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vsync_period = (lcdc->v_pulse_width +
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lcdc->v_back_porch +
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pinfo->yres + lcdc->yres_pad +
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lcdc->v_front_porch) * hsync_period;
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hsync_start_x =
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lcdc->h_pulse_width +
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lcdc->h_back_porch;
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hsync_end_x =
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hsync_period - lcdc->h_front_porch - 1;
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display_hctl = (hsync_end_x << 16) | hsync_start_x;
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display_vstart = (lcdc->v_pulse_width +
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lcdc->v_back_porch)
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* hsync_period + lcdc->hsync_skew;
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display_vend = vsync_period -
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(lcdc->v_front_porch * hsync_period)
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+lcdc->hsync_skew - 1;
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/* MDP_AXI_RDMASTER_CONFIG set all master to read from
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AXI port 0, that's the only port connected */
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writel(0x00290000, MDP_AXI_RDMASTER_CONFIG);
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writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
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writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
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/* Set up CMD_INTF_SEL, VIDEO_INTF_SEL,
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EXT_INTF_SEL, SEC_INTF_SEL, PRIM_INTF_SEL */
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writel(0x00000049, MDP_DISP_INTF_SEL);
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/* DMA P */
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writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
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/* write fb addr in MDP_DMA_P_BUF_ADDR */
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writel(fb->base, MDP_DMA_P_BUF_ADDR);
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/* write active region size*/
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mdp_rgb_size = (fb->height << 16) + fb->width;
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writel(mdp_rgb_size, MDP_DMA_P_SIZE);
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/* set Y-stride value in bytes */
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/* Y-stride is defined as the number of bytes
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in a line.
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*/
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writel((fb->stride * fb->bpp/8), MDP_DMA_P_BUF_Y_STRIDE);
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/* Start XY coordinates */
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writel(0, MDP_DMA_P_OUT_XY);
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if (fb->bpp == 16) {
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writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB |
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DMA_DITHER_EN | DMA_OUT_SEL_LCDC |
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DMA_IBUF_FORMAT_RGB565 | DMA_DSTC0G_8BITS |
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DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS,
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MDP_DMA_P_CONFIG);
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} else if (fb->bpp == 24) {
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writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB |
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DMA_DITHER_EN | DMA_OUT_SEL_LCDC |
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DMA_IBUF_FORMAT_RGB888 | DMA_DSTC0G_8BITS |
|
||
|
|
DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS,
|
||
|
|
MDP_DMA_P_CONFIG);
|
||
|
|
} else {
|
||
|
|
dprintf(CRITICAL, "Unsupported bpp detected!\n");
|
||
|
|
return ERR_INVALID_ARGS;
|
||
|
|
}
|
||
|
|
|
||
|
|
writel(hsync_period << 16 | lcdc->h_pulse_width,
|
||
|
|
MDP_DSI_VIDEO_HSYNC_CTL);
|
||
|
|
writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
|
||
|
|
writel(lcdc->v_pulse_width * hsync_period,
|
||
|
|
MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
|
||
|
|
writel(display_hctl,
|
||
|
|
MDP_DSI_VIDEO_DISPLAY_HCTL);
|
||
|
|
writel(display_vstart, MDP_DSI_VIDEO_DISPLAY_V_START);
|
||
|
|
writel(display_vend, MDP_DSI_VIDEO_DISPLAY_V_END);
|
||
|
|
|
||
|
|
if (lcdc->xres_pad) {
|
||
|
|
writel((1 << 31) |
|
||
|
|
(lcdc->h_back_porch + lcdc->h_pulse_width +
|
||
|
|
fb->width - 1) << 16 | lcdc->h_pulse_width +
|
||
|
|
lcdc->h_back_porch, MDP_DSI_VIDEO_ACTIVE_HCTL);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (pinfo->mipi.force_clk_lane_hs) {
|
||
|
|
uint32_t tmp;
|
||
|
|
|
||
|
|
tmp = readl_relaxed(MIPI_DSI_BASE + 0xA8);
|
||
|
|
tmp |= (1<<28);
|
||
|
|
writel_relaxed(tmp, MIPI_DSI_BASE + 0xA8);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int mdp_dsi_video_on()
|
||
|
|
{
|
||
|
|
int ret = NO_ERROR;
|
||
|
|
|
||
|
|
writel(0x00000001, MDP_DSI_VIDEO_EN);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int mdp_dsi_video_off()
|
||
|
|
{
|
||
|
|
if(!target_cont_splash_screen())
|
||
|
|
{
|
||
|
|
writel(0x00000000, MDP_DSI_VIDEO_EN);
|
||
|
|
mdelay(60);
|
||
|
|
writel(0x00000000, MDP_INTR_ENABLE);
|
||
|
|
writel(0x00000003, MDP_OVERLAYPROC0_CFG);
|
||
|
|
}
|
||
|
|
|
||
|
|
return NO_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
int mdp_dsi_cmd_off()
|
||
|
|
{
|
||
|
|
mdp_dma_off();
|
||
|
|
/*
|
||
|
|
* Allow sometime for the DMA channel to
|
||
|
|
* stop the data transfer
|
||
|
|
*/
|
||
|
|
mdelay(10);
|
||
|
|
writel(0x00000000, MDP_INTR_ENABLE);
|
||
|
|
writel(0x00000003, MDP_OVERLAYPROC0_CFG);
|
||
|
|
return NO_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
void mdp_set_revision(int rev)
|
||
|
|
{
|
||
|
|
mdp_rev = rev;
|
||
|
|
}
|
||
|
|
|
||
|
|
int mdp_get_revision()
|
||
|
|
{
|
||
|
|
return mdp_rev;
|
||
|
|
}
|