185 lines
6.5 KiB
C
185 lines
6.5 KiB
C
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/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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*
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* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _MSM7200_USB_H_
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#define _MSM7200_USB_H_
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#ifndef MSM_USB_BASE
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#define MSM_USB_BASE 0xA0800000
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#endif
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#define USB_ID (MSM_USB_BASE + 0x0000)
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#define USB_HWGENERAL (MSM_USB_BASE + 0x0004)
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#define USB_HWHOST (MSM_USB_BASE + 0x0008)
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#define USB_HWDEVICE (MSM_USB_BASE + 0x000C)
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#define USB_HWTXBUF (MSM_USB_BASE + 0x0010)
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#define USB_HWRXBUF (MSM_USB_BASE + 0x0014)
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#define USB_SBUSCFG (MSM_USB_BASE + 0x0090)
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#define USB_AHB_MODE (MSM_USB_BASE + 0x0098)
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#define USB_GENCONFIG_2 (MSM_USB_BASE + 0x00A0)
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#define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */
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#define USB_HCIVERSION (MSM_USB_BASE + 0x0102) /* 16 bit */
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#define USB_HCSPARAMS (MSM_USB_BASE + 0x0104)
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#define USB_HCCPARAMS (MSM_USB_BASE + 0x0108)
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#define USB_DCIVERSION (MSM_USB_BASE + 0x0120) /* 16 bit */
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#define USB_USBCMD (MSM_USB_BASE + 0x0140)
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#define USB_USBSTS (MSM_USB_BASE + 0x0144)
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#define USB_USBINTR (MSM_USB_BASE + 0x0148)
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#define USB_FRINDEX (MSM_USB_BASE + 0x014C)
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#define USB_DEVICEADDR (MSM_USB_BASE + 0x0154)
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#define USB_ENDPOINTLISTADDR (MSM_USB_BASE + 0x0158)
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#define USB_BURSTSIZE (MSM_USB_BASE + 0x0160)
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#define USB_TXFILLTUNING (MSM_USB_BASE + 0x0164)
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#define USB_ULPI_VIEWPORT (MSM_USB_BASE + 0x0170)
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#define USB_ENDPTNAK (MSM_USB_BASE + 0x0178)
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#define USB_ENDPTNAKEN (MSM_USB_BASE + 0x017C)
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#define USB_PORTSC (MSM_USB_BASE + 0x0184)
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#define USB_OTGSC (MSM_USB_BASE + 0x01A4)
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#define USB_USBMODE (MSM_USB_BASE + 0x01A8)
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#define USB_ENDPTSETUPSTAT (MSM_USB_BASE + 0x01AC)
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#define USB_ENDPTPRIME (MSM_USB_BASE + 0x01B0)
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#define USB_ENDPTFLUSH (MSM_USB_BASE + 0x01B4)
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#define USB_ENDPTSTAT (MSM_USB_BASE + 0x01B8)
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#define USB_ENDPTCOMPLETE (MSM_USB_BASE + 0x01BC)
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#define USB_ENDPTCTRL(n) (MSM_USB_BASE + 0x01C0 + (4 * (n)))
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#define USB_OTG_HS_PHY_CTRL (MSM_USB_BASE + 0x0240)
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#define USB_OTG_HS_PHY_SEC_CTRL (MSM_USB_BASE + 0x0278)
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/* ULPI registers */
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#define ULPI_MISC_A_READ 0x96
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#define ULPI_MISC_A_SET 0x97
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#define ULPI_MISC_A_CLEAR 0x98
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#define USBCMD_RESET 2
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#define USBCMD_ATTACH 1
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#define USBMODE_DEVICE 2
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#define USBMODE_HOST 3
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struct ept_queue_head {
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unsigned config;
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unsigned current; /* read-only */
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unsigned next;
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unsigned info;
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unsigned page0;
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unsigned page1;
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unsigned page2;
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unsigned page3;
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unsigned page4;
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unsigned reserved_0;
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unsigned char setup_data[8];
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unsigned reserved_1;
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unsigned reserved_2;
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unsigned reserved_3;
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unsigned reserved_4;
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};
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#define CONFIG_MAX_PKT(n) ((n) << 16)
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#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */
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#define CONFIG_IOS (1 << 15) /* IRQ on setup */
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struct ept_queue_item {
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unsigned next;
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unsigned info;
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unsigned page0;
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unsigned page1;
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unsigned page2;
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unsigned page3;
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unsigned page4;
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unsigned reserved;
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};
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#define TERMINATE 1
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#define INFO_BYTES(n) ((n) << 16)
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#define INFO_IOC (1 << 15)
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#define INFO_ACTIVE (1 << 7)
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#define INFO_HALTED (1 << 6)
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#define INFO_BUFFER_ERROR (1 << 5)
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#define INFO_TX_ERROR (1 << 3)
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#define STS_NAKI (1 << 16) /* */
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#define STS_SLI (1 << 8) /* R/WC - suspend state entered */
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#define STS_SRI (1 << 7) /* R/WC - SOF recv'd */
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#define STS_URI (1 << 6) /* R/WC - RESET recv'd - write to clear */
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#define STS_FRI (1 << 3) /* R/WC - Frame List Rollover */
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#define STS_PCI (1 << 2) /* R/WC - Port Change Detect */
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#define STS_UEI (1 << 1) /* R/WC - USB Error */
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#define STS_UI (1 << 0) /* R/WC - USB Transaction Complete */
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/* bits used in all the endpoint status registers */
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#define EPT_TX(n) (1 << ((n) + 16))
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#define EPT_RX(n) (1 << (n))
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#define CTRL_TXE (1 << 23)
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#define CTRL_TXR (1 << 22)
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#define CTRL_TXI (1 << 21)
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#define CTRL_TXD (1 << 17)
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#define CTRL_TXS (1 << 16)
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#define CTRL_RXE (1 << 7)
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#define CTRL_RXR (1 << 6)
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#define CTRL_RXI (1 << 5)
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#define CTRL_RXD (1 << 1)
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#define CTRL_RXS (1 << 0)
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#define CTRL_TXT_CTRL (0 << 18)
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#define CTRL_TXT_ISOCH (1 << 18)
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#define CTRL_TXT_BULK (2 << 18)
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#define CTRL_TXT_INT (3 << 18)
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#define CTRL_RXT_CTRL (0 << 2)
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#define CTRL_RXT_ISOCH (1 << 2)
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#define CTRL_RXT_BULK (2 << 2)
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#define CTRL_RXT_INT (3 << 2)
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#define GEN2_SESS_VLD_CTRL_EN (1 << 7)
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#define SESS_VLD_CTRL (1 << 25)
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/* ULPI bit map */
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#define ULPI_WAKEUP (1 << 31)
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#define ULPI_RUN (1 << 30)
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#define ULPI_WRITE (1 << 29)
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#define ULPI_READ (0 << 29)
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#define ULPI_STATE_NORMAL (1 << 27)
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#define ULPI_ADDR(n) (((n) & 255) << 16)
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#define ULPI_DATA(n) ((n) & 255)
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#define ULPI_DATA_READ(n) (((n) >> 8) & 255)
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#define ULPI_MISC_A_VBUSVLDEXTSEL (1 << 1)
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#define ULPI_MISC_A_VBUSVLDEXT (1 << 0)
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#endif
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