406 lines
11 KiB
ArmAsm
406 lines
11 KiB
ArmAsm
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/*
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* Copyright (c) 2008 Travis Geiselbrecht
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <asm.h>
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#include <arch/ops.h>
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#include <arch/defines.h>
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.text
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#if ARM_WITH_CACHE
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/* low level cache routines for various cpu families */
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#if ARM_CPU_ARM1136 || ARM_CPU_ARM926
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/* void arch_disable_cache(uint flags) */
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FUNCTION(arch_disable_cache)
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mov r12, #0 // zero register
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mrs r3, cpsr // save the old interrupt state
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#if ARM_ISA_ARMv6
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.word 0xf10c01c0 /* cpsid iaf */ // interrupts disabled
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#else
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orr r3, r3, #(1<<7)
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msr cpsr, r3
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#endif
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.Ldcache_disable:
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tst r0, #DCACHE
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beq .Licache_disable
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mrc p15, 0, r1, c1, c0, 0 // cr1
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tst r1, #(1<<2) // is the dcache already disabled?
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beq .Licache_disable
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bic r1, #(1<<2)
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mcr p15, 0, r1, c1, c0, 0 // disable dcache
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#if ARM_CPU_ARM1136
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mcr p15, 0, r12, c7, c14, 0 // clean & invalidate dcache
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#elif ARM_CPU_ARM926
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0:
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mrc p15, 0, r15, c7, c14, 3 // clean & invalidate dcache
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bne 0b
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#else
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#error whut?
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#endif
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mcr p15, 0, r0, c7, c10, 4 // data sync barrier (formerly drain write buffer)
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.Licache_disable:
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tst r0, #ICACHE
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beq .Ldone_disable
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mrc p15, 0, r1, c1, c0, 0 // cr1
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bic r1, #(1<<12)
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mcr p15, 0, r1, c1, c0, 0 // disable icache
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mcr p15, 0, r12, c7, c5, 0 // invalidate icache
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.Ldone_disable:
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msr cpsr, r3
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bx lr
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/* void arch_enable_cache(uint flags) */
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FUNCTION(arch_enable_cache)
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mov r12, #0 // zero register
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mrs r3, cpsr // save the old interrupt state
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#if ARM_ISA_ARMv6
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.word 0xf10c01c0 /* cpsid iaf */ // interrupts disabled
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#else
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orr r3, r3, #(1<<7)
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msr cpsr, r3
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#endif
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.Ldcache_enable:
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tst r0, #DCACHE
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beq .Licache_enable
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mrc p15, 0, r1, c1, c0, 0 // cr1
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tst r1, #(1<<2) // is the dcache already enabled?
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bne .Licache_enable
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mcr p15, 0, r12, c7, c6, 0 // invalidate dcache
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orr r1, #(1<<2)
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mcr p15, 0, r1, c1, c0, 0 // enable dcache
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.Licache_enable:
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tst r0, #ICACHE
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beq .Ldone_enable
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mcr p15, 0, r12, c7, c5, 0 // invalidate icache
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mrc p15, 0, r1, c1, c0, 0 // cr1
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orr r1, #(1<<12)
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mcr p15, 0, r1, c1, c0, 0 // enable icache
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.Ldone_enable:
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msr cpsr, r3
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bx lr
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#elif ARM_CPU_CORTEX_A8
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/* void arch_disable_cache(uint flags) */
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FUNCTION(arch_disable_cache)
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stmfd sp!, {r4-r11, lr}
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mov r7, r0 // save flags
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mrs r12, cpsr // save the old interrupt state
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.word 0xf10c01c0 /* cpsid iaf */ // interrupts disabled
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.Ldcache_disable:
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tst r7, #DCACHE
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beq .Licache_disable
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mrc p15, 0, r0, c1, c0, 0 // cr1
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tst r0, #(1<<2) // is the dcache already disabled?
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beq .Ldcache_already_disabled
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bic r0, #(1<<2)
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// make sure all data operations are completed
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dsb
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mcr p15, 0, r0, c1, c0, 0 // disable dcache
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// make sure previous instruction finishes before we clean and flush
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isb
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// flush and invalidate the dcache
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// NOTE: trashes a bunch of registers, can't be spilling stuff to the stack
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bl flush_invalidate_cache_v7
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b .Ldcache_disable_L2
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.Ldcache_already_disabled:
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// make sure all of the caches are invalidated
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// NOTE: trashes a bunch of registers, can't be spilling stuff to the stack
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bl invalidate_cache_v7
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.Ldcache_disable_L2:
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#if ARM_WITH_L2
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// disable the L2, if present
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mrc p15, 0, r0, c1, c0, 1 // aux cr1
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bic r0, #(1<<1)
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mcr p15, 0, r0, c1, c0, 1 // disable L2 dcache
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#endif
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.Licache_disable:
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tst r7, #ICACHE
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beq .Ldone_disable
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mrc p15, 0, r0, c1, c0, 0 // cr1
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bic r0, #(1<<12)
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mcr p15, 0, r0, c1, c0, 0 // disable icache
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// make sure previous instruction finishes
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isb
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.Ldone_disable:
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// make sure the icache is always invalidated
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 // invalidate icache to PoU
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// make sure that data is in sync
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dsb
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msr cpsr, r12
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ldmfd sp!, {r4-r11, pc}
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/* void arch_enable_cache(uint flags) */
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FUNCTION(arch_enable_cache)
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stmfd sp!, {r4-r11, lr}
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mov r7, r0 // save flags
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mrs r12, cpsr // save the old interrupt state
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.word 0xf10c01c0 /* cpsid iaf */ // interrupts disabled
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.Ldcache_enable:
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tst r7, #DCACHE
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beq .Licache_enable
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mrc p15, 0, r0, c1, c0, 0 // cr1
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tst r0, #(1<<2) // is the dcache already enabled?
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bne .Licache_enable
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// invalidate L1 and L2
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// NOTE: trashes a bunch of registers, can't be spilling stuff to the stack
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bl invalidate_cache_v7
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#if ARM_WITH_L2
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// enable the L2, if present
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mrc p15, 0, r0, c1, c0, 1 // aux cr1
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orr r0, #(1<<1)
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mcr p15, 0, r0, c1, c0, 1 // enable L2 dcache
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#endif
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mrc p15, 0, r0, c1, c0, 0 // cr1
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orr r0, #(1<<2)
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mcr p15, 0, r0, c1, c0, 0 // enable dcache
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.Licache_enable:
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tst r7, #ICACHE
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beq .Ldone_enable
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 // invalidate icache to PoU
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mrc p15, 0, r0, c1, c0, 0 // cr1
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orr r0, #(1<<12)
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mcr p15, 0, r0, c1, c0, 0 // enable icache
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.Ldone_enable:
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msr cpsr, r12
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ldmfd sp!, {r4-r11, pc}
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// flush & invalidate cache routine, trashes r0-r6, r9-r11
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flush_invalidate_cache_v7:
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DMB
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/* from ARMv7 manual, B2-17 */
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MRC p15, 1, R0, c0, c0, 1 // Read CLIDR
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ANDS R3, R0, #0x7000000
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MOV R3, R3, LSR #23 // Cache level value (naturally aligned)
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BEQ .Lfinished
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MOV R10, #0
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.Loop1:
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ADD R2, R10, R10, LSR #1 // Work out 3xcachelevel
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MOV R1, R0, LSR R2 // bottom 3 bits are the Cache type for this level
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AND R1, R1, #7 // get those 3 bits alone
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CMP R1, #2
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BLT .Lskip // no cache or only instruction cache at this level
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MCR p15, 2, R10, c0, c0, 0 // write the Cache Size selection register
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.word 0xf57ff06f // ISB // ISB to sync the change to the CacheSizeID reg
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MRC p15, 1, R1, c0, c0, 0 // reads current Cache Size ID register
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AND R2, R1, #0x7 // extract the line length field
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ADD R2, R2, #4 // add 4 for the line length offset (log2 16 bytes)
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LDR R4, =0x3FF
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ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
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CLZ R5, R4 // R5 is the bit position of the way size increment
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LDR R6, =0x00007FFF
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ANDS R6, R6, R1, LSR #13 // R6 is the max number of the index size (right aligned)
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.Loop2:
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MOV R9, R4 // R9 working copy of the max way size (right aligned)
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.Loop3:
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ORR R11, R10, R9, LSL R5 // factor in the way number and cache number into R11
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ORR R11, R11, R6, LSL R2 // factor in the index number
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MCR p15, 0, R11, c7, c14, 2 // clean & invalidate by set/way
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SUBS R9, R9, #1 // decrement the way number
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BGE .Loop3
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SUBS R6, R6, #1 // decrement the index
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BGE .Loop2
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.Lskip:
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ADD R10, R10, #2 // increment the cache number
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CMP R3, R10
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BGT .Loop1
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.Lfinished:
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mov r10, #0
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mcr p15, 2, r10, c0, c0, 0 // select cache level 0
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dsb
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.word 0xf57ff06f // isb
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bx lr
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// invalidate cache routine, trashes r0-r6, r9-r11
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invalidate_cache_v7:
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/* from ARMv7 manual, B2-17 */
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MRC p15, 1, R0, c0, c0, 1 // Read CLIDR
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ANDS R3, R0, #0x7000000
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MOV R3, R3, LSR #23 // Cache level value (naturally aligned)
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BEQ .Lfinished_invalidate
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MOV R10, #0
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.Loop1_invalidate:
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ADD R2, R10, R10, LSR #1 // Work out 3xcachelevel
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MOV R1, R0, LSR R2 // bottom 3 bits are the Cache type for this level
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AND R1, R1, #7 // get those 3 bits alone
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CMP R1, #2
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BLT .Lskip_invalidate // no cache or only instruction cache at this level
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MCR p15, 2, R10, c0, c0, 0 // write the Cache Size selection register
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.word 0xf57ff06f // ISB // ISB to sync the change to the CacheSizeID reg
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MRC p15, 1, R1, c0, c0, 0 // reads current Cache Size ID register
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AND R2, R1, #0x7 // extract the line length field
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ADD R2, R2, #4 // add 4 for the line length offset (log2 16 bytes)
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LDR R4, =0x3FF
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ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
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CLZ R5, R4 // R5 is the bit position of the way size increment
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LDR R6, =0x00007FFF
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ANDS R6, R6, R1, LSR #13 // R6 is the max number of the index size (right aligned)
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.Loop2_invalidate:
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MOV R9, R4 // R9 working copy of the max way size (right aligned)
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.Loop3_invalidate:
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ORR R11, R10, R9, LSL R5 // factor in the way number and cache number into R11
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ORR R11, R11, R6, LSL R2 // factor in the index number
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MCR p15, 0, R11, c7, c6, 2 // invalidate by set/way
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SUBS R9, R9, #1 // decrement the way number
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BGE .Loop3_invalidate
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SUBS R6, R6, #1 // decrement the index
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BGE .Loop2_invalidate
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.Lskip_invalidate:
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ADD R10, R10, #2 // increment the cache number
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CMP R3, R10
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BGT .Loop1_invalidate
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.Lfinished_invalidate:
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mov r10, #0
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mcr p15, 2, r10, c0, c0, 0 // select cache level 0
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dsb
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.word 0xf57ff06f // isb
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bx lr
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#else
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#error unhandled cpu
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#endif
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#if ARM_CPU_ARM926 || ARM_CPU_ARM1136 || ARM_CPU_CORTEX_A8
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/* shared cache flush routines */
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/* void arch_flush_cache_range(addr_t start, size_t len); */
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FUNCTION(arch_clean_cache_range)
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0:
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mcr p15, 0, r0, c7, c10, 1 // clean cache to PoC by MVA
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add r0, r0, #CACHE_LINE
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subs r1, r1, #CACHE_LINE
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bhs 0b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 // data sync barrier (formerly drain write buffer)
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||
|
|
bx lr
|
||
|
|
|
||
|
|
/* void arch_flush_invalidate_cache_range(addr_t start, size_t len); */
|
||
|
|
FUNCTION(arch_clean_invalidate_cache_range)
|
||
|
|
0:
|
||
|
|
mcr p15, 0, r0, c7, c14, 1 // clean & invalidate cache to PoC by MVA
|
||
|
|
add r0, r0, #CACHE_LINE
|
||
|
|
subs r1, r1, #CACHE_LINE
|
||
|
|
bhs 0b
|
||
|
|
|
||
|
|
mov r0, #0
|
||
|
|
mcr p15, 0, r0, c7, c10, 4 // data sync barrier (formerly drain write buffer)
|
||
|
|
|
||
|
|
bx lr
|
||
|
|
|
||
|
|
/* void arch_invalidate_cache_range(addr_t start, size_t len); */
|
||
|
|
FUNCTION(arch_invalidate_cache_range)
|
||
|
|
0:
|
||
|
|
/* invalidate cache line */
|
||
|
|
mcr p15, 0, r0, c7, c6, 1
|
||
|
|
add r0, r0, #CACHE_LINE
|
||
|
|
subs r1, r1, #CACHE_LINE
|
||
|
|
bhs 0b
|
||
|
|
mov r0, #0
|
||
|
|
/* data sync barrier (formerly drain write buffer*/
|
||
|
|
mcr p15, 0, r0, c7, c10, 4
|
||
|
|
bx lr
|
||
|
|
|
||
|
|
/* void arch_sync_cache_range(addr_t start, size_t len); */
|
||
|
|
FUNCTION(arch_sync_cache_range)
|
||
|
|
push { r14 }
|
||
|
|
bl arch_clean_cache_range
|
||
|
|
|
||
|
|
mov r0, #0
|
||
|
|
mcr p15, 0, r0, c7, c5, 0 // invalidate icache to PoU
|
||
|
|
|
||
|
|
pop { pc }
|
||
|
|
|
||
|
|
#else
|
||
|
|
#error unhandled cpu
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#else
|
||
|
|
|
||
|
|
/* no cache */
|
||
|
|
|
||
|
|
FUNCTION(arch_disable_cache)
|
||
|
|
bx lr
|
||
|
|
|
||
|
|
FUNCTION(arch_enable_cache)
|
||
|
|
bx lr
|
||
|
|
|
||
|
|
FUNCTION(arch_clean_cache_range)
|
||
|
|
bx lr
|
||
|
|
|
||
|
|
FUNCTION(arch_clean_invalidate_cache_range)
|
||
|
|
bx lr
|
||
|
|
|
||
|
|
FUNCTION(arch_sync_cache_range)
|
||
|
|
bx lr
|
||
|
|
|
||
|
|
#endif // ARM_WITH_CACHE
|
||
|
|
|