166 lines
4.2 KiB
C
166 lines
4.2 KiB
C
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#ifndef __HAL88XXRXDESC_H__
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#define __HAL88XXRXDESC_H__
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#if defined(_PC_) || defined(_PUMA6_)
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#ifdef FS
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#undef FS
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#endif
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#endif
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typedef struct _RX_DESC_88XX_
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{
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volatile u4Byte Dword0;
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volatile u4Byte Dword1;
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volatile u4Byte Dword2;
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volatile u4Byte Dword3;
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volatile u4Byte Dword4;
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volatile u4Byte Dword5;
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} RX_DESC_88XX, *PRX_DESC_88XX;
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#define SIZE_RXDESC_88XX 24
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typedef enum _HCI_RX_DMA_QUEUE_88XX_
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{
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HCI_RX_DMA_QUEUE_Q0 = 0,
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HCI_RX_DMA_QUEUE_MAX_NUM
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} HCI_RX_DMA_QUEUE_88XX, *PHCI_RX_DMA_QUEUE_88XX;
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typedef struct _RX_BUFFER_DESCRIPTOR_
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{
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u4Byte Dword0;
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u4Byte Dword1;
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#if TXBD_SEG_32_64_SEL
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u4Byte Dword2;
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u4Byte Dword3;
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#endif
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} RX_BUFFER_DESCRIPTOR, *PRX_BUFFER_DESCRIPTOR;
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typedef struct _HCI_RX_DMA_QUEUE_STRUCT_88XX_
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{
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PRX_BUFFER_DESCRIPTOR pRXBD_head;
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#ifdef CONFIG_NET_PCI
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unsigned long rxbd_dma_addr;
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#endif
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u2Byte hw_idx; //Mapping to HW register
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u2Byte host_idx; //Mapping to HW register
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//Special case:
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// If we can't allocate a new SKB(RXDESC+Payload) to mapping RXBD,
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// we still need to maintain a pointer in order to recieve RxPkt continuously
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u2Byte cur_host_idx; // the index to indicate the next location that we have received RxPkt
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#if CFG_HAL_DELAY_REFILL_RX_BUF
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u2Byte rxbd_ok_cnt;
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#endif
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u2Byte total_rxbd_num;
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u2Byte avail_rxbd_num;
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u4Byte reg_rwptr_idx;
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#if RXBD_READY_CHECK_METHOD
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// reset signal from 0x100[1], CR[HCI_RXDMA_EN]
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u2Byte rxtag_seq_num;
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#endif
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} HCI_RX_DMA_QUEUE_STRUCT_88XX, *PHCI_RX_DMA_QUEUE_STRUCT_88XX;
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typedef struct _HCI_RX_DMA_MANAGER_88XX_
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{
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HCI_RX_DMA_QUEUE_STRUCT_88XX rx_queue[HCI_RX_DMA_QUEUE_MAX_NUM];
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} HCI_RX_DMA_MANAGER_88XX, *PHCI_RX_DMA_MANAGER_88XX;
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typedef struct _RX_DESC_STATUS_88XX_
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{
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// RXBD
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BOOLEAN FS;
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BOOLEAN LS;
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u2Byte RXBuffSize;
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#if CFG_HAL_DBG
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u2Byte remaining_pkt_len;
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u4Byte pktBufAddr[32];
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u2Byte pktBufLen[32];
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u2Byte pktNum;
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#endif
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//4 Note: value below Only valid in FS=1
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// Dword0
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u2Byte PKT_LEN;
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BOOLEAN CRC32;
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BOOLEAN ICVERR;
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u1Byte DRV_INFO_SIZE;
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u1Byte SECURITY;
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u1Byte SHIFT;
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BOOLEAN PHYST;
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BOOLEAN SWDEC;
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BOOLEAN EOR;
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// Dword 1
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BOOLEAN PAGGR;
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// Dword 2
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BOOLEAN C2HPkt;
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// Dowrd 3
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u1Byte RX_RATE;
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// Dword 4
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BOOLEAN OFDM_SGI;
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BOOLEAN CCK_SPLCP;
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BOOLEAN LDPC;
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BOOLEAN STBC;
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BOOLEAN NOT_SOUNDING;
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u1Byte BW;
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#if CFG_HAL_HW_FILL_MACID
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u1Byte rxMACID;
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#endif
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} RX_DESC_STATUS_88XX, *PRX_DESC_STATUS_88XX;
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RT_STATUS
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QueryRxDesc88XX (
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IN HAL_PADAPTER Adapter,
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IN u4Byte queueIndex,
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IN pu1Byte pBufAddr,
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OUT PVOID pRxDescStatus
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);
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RT_STATUS
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UpdateRXBDInfo88XX(
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IN HAL_PADAPTER Adapter,
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IN u4Byte queueIndex, //HCI_RX_DMA_QUEUE_88XX
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IN u2Byte rxbd_idx,
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IN pu1Byte pBuf,
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IN PVOID Callback, // callback function
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IN BOOLEAN bInit
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);
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u2Byte
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UpdateRXBDHWIdx88XX(
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IN HAL_PADAPTER Adapter,
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IN u4Byte queueIndex
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);
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VOID
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UpdateRXBDHostIdx88XX (
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IN HAL_PADAPTER Adapter,
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IN u4Byte queueIndex, //HCI_TX_DMA_QUEUE_88XX
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IN u4Byte Count
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);
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RT_STATUS
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PrepareRXBD88XX(
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IN HAL_PADAPTER Adapter,
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IN u2Byte bufferLen,
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IN PVOID Callback // callback function
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);
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void DumpRxBDesc88XX(
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IN HAL_PADAPTER Adapter,
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#ifdef CONFIG_RTL_PROC_NEW
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IN struct seq_file *s,
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#endif
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IN u4Byte q_num
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);
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#endif //#ifndef __HAL88XXRXDESC_H__
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