272 lines
9.1 KiB
C
272 lines
9.1 KiB
C
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#ifndef __HAL_COM_RXDESC_H__
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#define __HAL_COM_RXDESC_H__
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/*-------------------------Modification Log-----------------------------------
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-------------------------Modification Log-----------------------------------*/
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/*--------------------------Include File--------------------------------------*/
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#include "HalHWCfg.h"
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/*--------------------------Include File--------------------------------------*/
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#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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//3 RX Buffer Descriptor
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//RXBD Desc bit Mask & Shift
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//Dword 0 MSK
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#define RXBD_DW0_RXBUFSIZE_MSK 0x3FFF
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#define RXBD_DW0_LS_MSK 0x1
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#define RXBD_DW0_FS_MSK 0x1
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#define RXBD_DW0_TOTALRXPKTSIZE_MSK 0xFFFF
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//Dword 0 SHIFT
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#define RXBD_DW0_RXBUFSIZE_SH 0
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#define RXBD_DW0_LS_SH 14
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#define RXBD_DW0_FS_SH 15
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#define RXBD_DW0_TOTALRXPKTSIZE_SH 16
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//Dword 1 MSK
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#define RXBD_DW1_PHYADDR_LOW_MSK 0xFFFFFFFF
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//Dword 1 SHIFT
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#define RXBD_DW1_PHYADDR_LOW_SH 0
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//Dword 2 MSK
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#define RXBD_DW2_PHYADDR_HIGH_MSK 0xFFFFFFFF
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//Dword 2 SHIFT
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#define RXBD_DW2_PHYADDR_HIGH_SH 0
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//Dword 3 MSK
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#define RXBD_DW3_PHYADDR_RSVD_MSK 0xFFFFFFFF
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//Dword 3 SHIFT
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#define RXBD_DW3_PHYADDR_RSVD_SH 0
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//3 RX WiFi Info
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//======RX Desc bit Mask & Shift=======
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//Dword0
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#define RX_DW0_PKT_LEN_MSK 0x3FFF
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#define RX_DW0_CRC32_MSK 0x1
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#define RX_DW0_ICVERR_MSK 0x1
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#define RX_DW0_DRV_INFO_SIZE_MSK 0xF
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#define RX_DW0_SECURITY_MSK 0x7
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#define RX_DW0_QOS_MSK 0x1
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#define RX_DW0_SHIFT_MSK 0x3
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#define RX_DW0_PHYST_MSK 0x1
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#define RX_DW0_SWDEC_MSK 0x1
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#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#define RX_DW0_RSVD28_29_MSK 0x3
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#endif
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#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
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#define RX_DW0_PHYPKTIDC_MSK 0x1
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#define RX_DW0_RSVD_29_MSK 0x1
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#endif
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#define RX_DW0_EOR_MSK 0x1
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#define RX_DW0_OWN_MSK 0x1
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//Dword0
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#define RX_DW0_PKT_LEN_SH 0
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#define RX_DW0_CRC32_SH 14
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#define RX_DW0_ICVERR_SH 15
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#define RX_DW0_DRV_INFO_SIZE_SH 16
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#define RX_DW0_SECURITY_SH 20
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#define RX_DW0_QOS_SH 23
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#define RX_DW0_SHIFT_SH 24
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#define RX_DW0_PHYST_SH 26
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#define RX_DW0_SWDEC_SH 27
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#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#define RX_DW0_RSVD28_29_SH 28
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#endif
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#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
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#define RX_DW0_PHYPKTIDC_SH 28
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#define RX_DW0_RSVD29_SH 29
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#endif
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#define RX_DW0_EOR_SH 30
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#define RX_DW0_RSVD31_SH 31
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//Dword1
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#define RX_DW1_MACID_MSK 0x7F
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#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#define RX_DW1_RSVD7_MSK 0x1
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#endif
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#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
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#define RX_DW1_EXT_SECTYPE_MSK 0x1
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#endif
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#define RX_DW1_TID_MSK 0xF
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#define RX_DW1_MACID_VLD_MSK 0x1
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#define RX_DW1_AMSDU_MSK 0x1
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#define RX_DW1_RXID_MATCH_MSK 0x1
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#define RX_DW1_PAGGR_MSK 0x1
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#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#define RX_DW1_A1_FIT_MSK 0xF
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#endif
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#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
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#define RX_DW1_RSVD_16_19_MSK 0xF
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#endif
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#define RX_DW1_CHKERR_MSK 0x1
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#define RX_DW1_RX_IPV_MSK 0x1
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#define RX_DW1_RX_IS_TCP_UDP_MSK 0x1
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#define RX_DW1_CHK_VLD_MSK 0x1
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#define RX_DW1_PAM_MSK 0x1
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#define RX_DW1_PWR_MSK 0x1
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#define RX_DW1_MD_MSK 0x1
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#define RX_DW1_MF_MSK 0x1
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#define RX_DW1_TYPE_MSK 0x3
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#define RX_DW1_MC_MSK 0x1
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#define RX_DW1_BC_MSK 0x1
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//Dword1
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#define RX_DW1_MACID_SH 0
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#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#define RX_DW1_RSVD7_SH 7
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#endif
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#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
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#define RX_DW1_EXT_SECTYPE_SH 7
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#endif
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#define RX_DW1_TID_SH 8
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#define RX_DW1_MACID_VLD_SH 12
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#define RX_DW1_AMSDU_SH 13
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#define RX_DW1_RXID_MATCH_SH 14
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#define RX_DW1_PAGGR_SH 15
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#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#define RX_DW1_A1_FIT_SH 16
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#endif
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#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
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#define RX_DW1_RSVD_16_19_SH 16
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#endif
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#define RX_DW1_CHKERR_SH 20
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#define RX_DW1_RX_IPV_SH 21
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#define RX_DW1_RX_IS_TCP_UDP_SH 22
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#define RX_DW1_CHK_VLD_SH 23
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#define RX_DW1_PAM_SH 24
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#define RX_DW1_PWR_SH 25
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#define RX_DW1_MD_SH 26
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#define RX_DW1_MF_SH 27
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#define RX_DW1_TYPE_SH 28
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#define RX_DW1_MC_SH 30
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#define RX_DW1_BC_SH 31
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//Dword2
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#define RX_DW2_SEQ_MSK 0xFFF
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#define RX_DW2_FRAG_MSK 0xF
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#define RX_DW2_RX_IS_QOS_MSK 0x1
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#define RX_DW2_RSVD17_MSK 0x1
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#define RX_DW2_WLANHD_IV_LEN_MSK 0x3F
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#define RX_DW2_HWRSVD_MSK 0xF
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#define RX_DW2_C2HPKT_MSK 0x1
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#define RX_DW2_RSVD29_30_MSK 0x3
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#define RX_DW2_FCS_OK_MSK 0x1
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//Dword2
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#define RX_DW2_SEQ_SH 0
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#define RX_DW2_FRAG_SH 12
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#define RX_DW2_RX_IS_QOS_SH 16
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#define RX_DW2_RSVD17_SH 17
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#define RX_DW2_WLANHD_IV_LEN_SH 18
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#define RX_DW2_HWRSVD_SH 24
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#define RX_DW2_C2HPKT_SH 28
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#define RX_DW2_RSVD29_30_SH 29
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#define RX_DW2_FCS_OK_SH 31
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//Dword3
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#define RX_DW3_RX_RATE_MSK 0x7F
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#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#define RX_DW3_RSVD7_9_MSK 0x7
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#endif
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#define RX_DW3_HTC_MSK 0x1
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#define RX_DW3_EOSP_MSK 0x1
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#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
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#define RX_DW3_BSSID_FIT_MSK 0x7
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#else
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#define RX_DW3_BSSID_FIT_MSK 0x3
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#endif
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#define RX_DW3_RSVD14_15_MSK 0x3
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#define RX_DW3_DMA_AGG_NUM_MSK 0xFF
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#define RX_DW3_RSVD24_28_MSK 0x1F
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#define RX_DW3_PATTERN_MATCH_MSK 0x1
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#define RX_DW3_UNICAST_MSK 0x1
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#define RX_DW3_MAGIC_WAKE_MSK 0x1
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//Dword3
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#define RX_DW3_RX_RATE_SH 0
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#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#define RX_DW3_RSVD7_9_SH 7
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#endif
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#define RX_DW3_HTC_SH 10
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#define RX_DW3_EOSP_SH 11
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#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
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#define RX_DW3_BSSID_FIT_SH 7
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#else
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#define RX_DW3_BSSID_FIT_SH 12
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#endif
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#define RX_DW3_RSVD14_15_SH 14
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#define RX_DW3_DMA_AGG_NUM_SH 16
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#define RX_DW3_RSVD24_28_SH 24
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#define RX_DW3_PATTERN_MATCH_SH 29
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#define RX_DW3_UNICAST_SH 30
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#define RX_DW3_MAGIC_WAKE_SH 31
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//Dword4
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#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#define RX_DW4_OFDM_SGI_MSK 0x1
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#define RX_DW4_CCK_SPLCP_MSK 0x1
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#define RX_DW4_LDPC_MSK 0x1
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#define RX_DW4_STBC_MSK 0x1
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#define RX_DW4_NOT_SOUNDING_MSK 0x1
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#define RX_DW4_BW_MSK 0x3
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#define RX_DW4_RSVD6_31_MSK 0x3FFFFFF
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#endif //#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
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#define RX_DW4_PATTERN_IDX_MSK 0xFF
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#define RX_DW4_RXEOF_MSK 0x1
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#define RX_DW4_RX_SCRMBLER_MSK 0x7F
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#define RX_DW4_RX_PRE_NDP_VLD_MSK 0x1
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#define RX_DW4_MACID_MSK 0x7F
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#define RX_DW4_A1_FIT_MSK 0x1F
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#define RX_DW4_RSVD29_31_MSK 0x7
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#endif //#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
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//Dword4
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#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#define RX_DW4_OFDM_SGI_SH 0
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#define RX_DW4_CCK_SPLCP_SH 0
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#define RX_DW4_LDPC_SH 1
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#define RX_DW4_STBC_SH 2
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#define RX_DW4_NOT_SOUNDING_SH 3
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#define RX_DW4_BW_SH 4
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#define RX_DW4_RSVD6_31_SH 6
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#endif //#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
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#define RX_DW4_PATTERN_IDX_SH 0
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#define RX_DW4_RXEOF_SH 8
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#define RX_DW4_RX_SCRMBLER_SH 9
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#define RX_DW4_RX_PRE_NDP_VLD_SH 16
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#define RX_DW4_MACID_SH 17
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#define RX_DW4_A1_FIT_SH 24
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#define RX_DW4_RSVD29_31_SH 29
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#endif //#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
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//Dword5
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#define RX_DW5_TSFL_MSK 0xFFFFFFFF
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//Dword5
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#define RX_DW5_TSFL_SH 0
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#endif //CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
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#endif //__HAL_COM_RXDESC_H__
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