2024-09-09 08:52:07 +00:00
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/*
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* (C) 2010,2011 Thomas Renninger <trenn@suse.de>, Novell Inc.
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*
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* Licensed under the terms of the GNU GPL License version 2.
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*
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* Miscellaneous helpers which do not fit or are worth
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* to put into separate headers
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*/
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#ifndef __CPUPOWERUTILS_HELPERS__
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#define __CPUPOWERUTILS_HELPERS__
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#include <libintl.h>
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#include <locale.h>
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#include "helpers/bitmask.h"
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/* Internationalization ****************************/
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#ifdef NLS
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#define _(String) gettext(String)
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#ifndef gettext_noop
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#define gettext_noop(String) String
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#endif
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#define N_(String) gettext_noop(String)
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#else /* !NLS */
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#define _(String) String
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#define N_(String) String
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#endif
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/* Internationalization ****************************/
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extern int run_as_root;
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extern struct bitmask *cpus_chosen;
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/* Global verbose (-d) stuff *********************************/
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/*
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* define DEBUG via global Makefile variable
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* Debug output is sent to stderr, do:
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* cpupower monitor 2>/tmp/debug
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* to split debug output away from normal output
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*/
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#ifdef DEBUG
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extern int be_verbose;
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#define dprint(fmt, ...) { \
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if (be_verbose) { \
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fprintf(stderr, "%s: " fmt, \
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__func__, ##__VA_ARGS__); \
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} \
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}
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#else
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static inline void dprint(const char *fmt, ...) { }
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#endif
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extern int be_verbose;
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/* Global verbose (-v) stuff *********************************/
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/* cpuid and cpuinfo helpers **************************/
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enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL,
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X86_VENDOR_AMD, X86_VENDOR_MAX};
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#define CPUPOWER_CAP_INV_TSC 0x00000001
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#define CPUPOWER_CAP_APERF 0x00000002
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#define CPUPOWER_CAP_AMD_CBP 0x00000004
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#define CPUPOWER_CAP_PERF_BIAS 0x00000008
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#define CPUPOWER_CAP_HAS_TURBO_RATIO 0x00000010
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#define CPUPOWER_CAP_IS_SNB 0x00000020
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#define CPUPOWER_CAP_INTEL_IDA 0x00000040
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#define MAX_HW_PSTATES 10
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struct cpupower_cpu_info {
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enum cpupower_cpu_vendor vendor;
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unsigned int family;
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unsigned int model;
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unsigned int stepping;
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/* CPU capabilities read out from cpuid */
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unsigned long long caps;
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};
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/* get_cpu_info
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*
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* Extract CPU vendor, family, model, stepping info from /proc/cpuinfo
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*
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* Returns 0 on success or a negativ error code
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* Only used on x86, below global's struct values are zero/unknown on
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* other archs
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*/
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extern int get_cpu_info(unsigned int cpu, struct cpupower_cpu_info *cpu_info);
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extern struct cpupower_cpu_info cpupower_cpu_info;
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/* cpuid and cpuinfo helpers **************************/
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2024-09-09 08:57:42 +00:00
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struct cpuid_core_info {
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int pkg;
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int core;
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int cpu;
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/* flags */
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unsigned int is_online:1;
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};
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2024-09-09 08:52:07 +00:00
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/* CPU topology/hierarchy parsing ******************/
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struct cpupower_topology {
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/* Amount of CPU cores, packages and threads per core in the system */
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unsigned int cores;
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unsigned int pkgs;
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unsigned int threads; /* per core */
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/* Array gets mallocated with cores entries, holding per core info */
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2024-09-09 08:57:42 +00:00
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struct cpuid_core_info *core_info;
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2024-09-09 08:52:07 +00:00
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};
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extern int get_cpu_topology(struct cpupower_topology *cpu_top);
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extern void cpu_topology_release(struct cpupower_topology cpu_top);
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2024-09-09 08:57:42 +00:00
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2024-09-09 08:52:07 +00:00
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/* CPU topology/hierarchy parsing ******************/
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/* X86 ONLY ****************************************/
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#if defined(__i386__) || defined(__x86_64__)
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#include <pci/pci.h>
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/* Read/Write msr ****************************/
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extern int read_msr(int cpu, unsigned int idx, unsigned long long *val);
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extern int write_msr(int cpu, unsigned int idx, unsigned long long val);
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extern int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val);
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extern int msr_intel_get_perf_bias(unsigned int cpu);
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extern unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu);
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/* Read/Write msr ****************************/
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/* PCI stuff ****************************/
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extern int amd_pci_get_num_boost_states(int *active, int *states);
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extern struct pci_dev *pci_acc_init(struct pci_access **pacc, int domain,
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int bus, int slot, int func, int vendor,
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int dev);
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extern struct pci_dev *pci_slot_func_init(struct pci_access **pacc,
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int slot, int func);
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/* PCI stuff ****************************/
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/* AMD HW pstate decoding **************************/
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extern int decode_pstates(unsigned int cpu, unsigned int cpu_family,
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int boost_states, unsigned long *pstates, int *no);
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/* AMD HW pstate decoding **************************/
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extern int cpufreq_has_boost_support(unsigned int cpu, int *support,
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int *active, int * states);
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/*
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* CPUID functions returning a single datum
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*/
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unsigned int cpuid_eax(unsigned int op);
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unsigned int cpuid_ebx(unsigned int op);
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unsigned int cpuid_ecx(unsigned int op);
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unsigned int cpuid_edx(unsigned int op);
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/* cpuid and cpuinfo helpers **************************/
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/* X86 ONLY ********************************************/
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#else
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static inline int decode_pstates(unsigned int cpu, unsigned int cpu_family,
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int boost_states, unsigned long *pstates,
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int *no)
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{ return -1; };
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static inline int read_msr(int cpu, unsigned int idx, unsigned long long *val)
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{ return -1; };
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static inline int write_msr(int cpu, unsigned int idx, unsigned long long val)
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{ return -1; };
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static inline int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val)
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{ return -1; };
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static inline int msr_intel_get_perf_bias(unsigned int cpu)
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{ return -1; };
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static inline unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu)
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{ return 0; };
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/* Read/Write msr ****************************/
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static inline int cpufreq_has_boost_support(unsigned int cpu, int *support,
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int *active, int * states)
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{ return -1; }
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/* cpuid and cpuinfo helpers **************************/
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static inline unsigned int cpuid_eax(unsigned int op) { return 0; };
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static inline unsigned int cpuid_ebx(unsigned int op) { return 0; };
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static inline unsigned int cpuid_ecx(unsigned int op) { return 0; };
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static inline unsigned int cpuid_edx(unsigned int op) { return 0; };
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#endif /* defined(__i386__) || defined(__x86_64__) */
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#endif /* __CPUPOWERUTILS_HELPERS__ */
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