2024-09-09 08:52:07 +00:00
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/*
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* linux/include/linux/mmc/host.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Host driver specific definitions.
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*/
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#ifndef LINUX_MMC_HOST_H
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#define LINUX_MMC_HOST_H
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#include <linux/leds.h>
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#include <linux/mutex.h>
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#include <linux/sched.h>
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#include <linux/device.h>
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#include <linux/devfreq.h>
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#include <linux/fault-inject.h>
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#include <linux/mmc/core.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/pm.h>
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#define MMC_AUTOSUSPEND_DELAY_MS 3000
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struct mmc_ios {
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unsigned int clock; /* clock rate */
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unsigned int old_rate; /* saved clock rate */
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unsigned long clk_ts; /* time stamp of last updated clock */
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unsigned short vdd;
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/* vdd stores the bit number of the selected voltage range from below. */
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unsigned char bus_mode; /* command output mode */
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#define MMC_BUSMODE_OPENDRAIN 1
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#define MMC_BUSMODE_PUSHPULL 2
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unsigned char chip_select; /* SPI chip select */
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#define MMC_CS_DONTCARE 0
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#define MMC_CS_HIGH 1
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#define MMC_CS_LOW 2
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unsigned char power_mode; /* power supply mode */
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#define MMC_POWER_OFF 0
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#define MMC_POWER_UP 1
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#define MMC_POWER_ON 2
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#define MMC_POWER_UNDEFINED 3
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unsigned char bus_width; /* data bus width */
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#define MMC_BUS_WIDTH_1 0
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#define MMC_BUS_WIDTH_4 2
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#define MMC_BUS_WIDTH_8 3
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unsigned char timing; /* timing specification used */
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#define MMC_TIMING_LEGACY 0
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#define MMC_TIMING_MMC_HS 1
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#define MMC_TIMING_SD_HS 2
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#define MMC_TIMING_UHS_SDR12 3
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#define MMC_TIMING_UHS_SDR25 4
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#define MMC_TIMING_UHS_SDR50 5
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#define MMC_TIMING_UHS_SDR104 6
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#define MMC_TIMING_UHS_DDR50 7
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#define MMC_TIMING_MMC_DDR52 8
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#define MMC_TIMING_MMC_HS200 9
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#define MMC_TIMING_MMC_HS400 10
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unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */
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#define MMC_SIGNAL_VOLTAGE_330 0
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#define MMC_SIGNAL_VOLTAGE_180 1
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#define MMC_SIGNAL_VOLTAGE_120 2
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unsigned char drv_type; /* driver type (A, B, C, D) */
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#define MMC_SET_DRIVER_TYPE_B 0
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#define MMC_SET_DRIVER_TYPE_A 1
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#define MMC_SET_DRIVER_TYPE_C 2
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#define MMC_SET_DRIVER_TYPE_D 3
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};
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/* states to represent load on the host */
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enum mmc_load {
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MMC_LOAD_HIGH,
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MMC_LOAD_LOW,
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};
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struct mmc_cmdq_host_ops {
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int (*init)(struct mmc_host *host);
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int (*enable)(struct mmc_host *host);
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void (*disable)(struct mmc_host *host, bool soft);
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int (*request)(struct mmc_host *host, struct mmc_request *mrq);
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void (*post_req)(struct mmc_host *host, int tag, int err);
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int (*halt)(struct mmc_host *host, bool halt);
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void (*reset)(struct mmc_host *host, bool soft);
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void (*dumpstate)(struct mmc_host *host);
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};
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struct mmc_host_ops {
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int (*init)(struct mmc_host *host);
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/*
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* 'enable' is called when the host is claimed and 'disable' is called
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* when the host is released. 'enable' and 'disable' are deprecated.
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*/
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int (*enable)(struct mmc_host *host);
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int (*disable)(struct mmc_host *host);
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/*
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* It is optional for the host to implement pre_req and post_req in
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* order to support double buffering of requests (prepare one
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* request while another request is active).
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* pre_req() must always be followed by a post_req().
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* To undo a call made to pre_req(), call post_req() with
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* a nonzero err condition.
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*/
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void (*post_req)(struct mmc_host *host, struct mmc_request *req,
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int err);
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void (*pre_req)(struct mmc_host *host, struct mmc_request *req,
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bool is_first_req);
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void (*request)(struct mmc_host *host, struct mmc_request *req);
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/*
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* Avoid calling these three functions too often or in a "fast path",
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* since underlaying controller might implement them in an expensive
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* and/or slow way.
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*
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* Also note that these functions might sleep, so don't call them
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* in the atomic contexts!
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*
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* Return values for the get_ro callback should be:
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* 0 for a read/write card
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* 1 for a read-only card
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* -ENOSYS when not supported (equal to NULL callback)
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* or a negative errno value when something bad happened
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*
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* Return values for the get_cd callback should be:
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* 0 for a absent card
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* 1 for a present card
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* -ENOSYS when not supported (equal to NULL callback)
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* or a negative errno value when something bad happened
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*/
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void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios);
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int (*get_ro)(struct mmc_host *host);
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int (*get_cd)(struct mmc_host *host);
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void (*enable_sdio_irq)(struct mmc_host *host, int enable);
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/* optional callback for HC quirks */
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void (*init_card)(struct mmc_host *host, struct mmc_card *card);
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int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios);
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/* Check if the card is pulling dat[0:3] low */
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int (*card_busy)(struct mmc_host *host);
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/* The tuning command opcode value is different for SD and eMMC cards */
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int (*execute_tuning)(struct mmc_host *host, u32 opcode);
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/* Prepare HS400 target operating frequency depending host driver */
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int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios);
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int (*enhanced_strobe)(struct mmc_host *host);
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int (*select_drive_strength)(unsigned int max_dtr, int host_drv, int card_drv);
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void (*hw_reset)(struct mmc_host *host);
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void (*card_event)(struct mmc_host *host);
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/*
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* Optional callback to support controllers with HW issues for multiple
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* I/O. Returns the number of supported blocks for the request.
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*/
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int (*multi_io_quirk)(struct mmc_card *card,
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unsigned int direction, int blk_size);
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unsigned long (*get_max_frequency)(struct mmc_host *host);
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unsigned long (*get_min_frequency)(struct mmc_host *host);
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int (*notify_load)(struct mmc_host *, enum mmc_load);
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void (*notify_halt)(struct mmc_host *mmc, bool halt);
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void (*force_err_irq)(struct mmc_host *host, u64 errmask);
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};
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struct mmc_card;
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struct device;
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struct mmc_cmdq_req {
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unsigned int cmd_flags;
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u32 blk_addr;
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/* active mmc request */
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struct mmc_request mrq;
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struct mmc_data data;
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struct mmc_command cmd;
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#define DCMD (1 << 0)
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#define QBR (1 << 1)
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#define DIR (1 << 2)
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#define PRIO (1 << 3)
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#define REL_WR (1 << 4)
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#define DAT_TAG (1 << 5)
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#define FORCED_PRG (1 << 6)
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unsigned int cmdq_req_flags;
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unsigned int resp_idx;
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unsigned int resp_arg;
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unsigned int dev_pend_tasks;
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bool resp_err;
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int tag; /* used for command queuing */
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u8 ctx_id;
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};
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struct mmc_async_req {
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/* active mmc request */
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struct mmc_request *mrq;
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/*
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* Check error status of completed mmc request.
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* Returns 0 if success otherwise non zero.
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*/
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int (*err_check) (struct mmc_card *, struct mmc_async_req *);
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};
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/**
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* struct mmc_slot - MMC slot functions
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*
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* @cd_irq: MMC/SD-card slot hotplug detection IRQ or -EINVAL
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* @lock: protect the @handler_priv pointer
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* @handler_priv: MMC/SD-card slot context
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*
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* Some MMC/SD host controllers implement slot-functions like card and
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* write-protect detection natively. However, a large number of controllers
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* leave these functions to the CPU. This struct provides a hook to attach
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* such slot-function drivers.
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*/
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struct mmc_slot {
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int cd_irq;
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struct mutex lock;
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void *handler_priv;
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};
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/**
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* mmc_cmdq_context_info - describes the contexts of cmdq
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* @active_reqs requests being processed
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* @data_active_reqs data requests being processed
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* @curr_state state of cmdq engine
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* @cmdq_ctx_lock acquire this before accessing this structure
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* @queue_empty_wq workqueue for waiting for all
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* the outstanding requests to be completed
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* @wait waiting for all conditions described in
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* mmc_cmdq_ready_wait to be satisified before
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* issuing the new request to LLD.
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*/
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struct mmc_cmdq_context_info {
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unsigned long active_reqs; /* in-flight requests */
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unsigned long data_active_reqs; /* in-flight data requests */
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unsigned long curr_state;
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#define CMDQ_STATE_ERR 0
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#define CMDQ_STATE_DCMD_ACTIVE 1
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#define CMDQ_STATE_HALT 2
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#define CMDQ_STATE_CQ_DISABLE 3
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#define CMDQ_STATE_REQ_TIMED_OUT 4
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wait_queue_head_t queue_empty_wq;
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wait_queue_head_t wait;
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int active_small_sector_read_reqs;
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};
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/**
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* mmc_context_info - synchronization details for mmc context
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* @is_done_rcv wake up reason was done request
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* @is_new_req wake up reason was new request
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* @is_waiting_last_req mmc context waiting for single running request
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* @wait wait queue
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* @lock lock to protect data fields
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*/
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struct mmc_context_info {
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bool is_done_rcv;
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bool is_new_req;
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bool is_waiting_last_req;
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wait_queue_head_t wait;
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spinlock_t lock;
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};
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struct regulator;
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struct mmc_supply {
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struct regulator *vmmc; /* Card power supply */
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struct regulator *vqmmc; /* Optional Vccq supply */
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};
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enum dev_state {
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DEV_SUSPENDING = 1,
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DEV_SUSPENDED,
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DEV_RESUMED,
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};
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/**
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* struct mmc_devfeq_clk_scaling - main context for MMC clock scaling logic
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*
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* @lock: spinlock to protect statistics
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* @devfreq: struct that represent mmc-host as a client for devfreq
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* @devfreq_profile: MMC device profile, mostly polling interval and callbacks
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* @ondemand_gov_data: struct supplied to ondemmand governor (thresholds)
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* @state: load state, can be HIGH or LOW. used to notify mmc_host_ops callback
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* @start_busy: timestamped armed once a data request is started
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* @measure_interval_start: timestamped armed once a measure interval started
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* @devfreq_abort: flag to sync between different contexts relevant to devfreq
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* @skip_clk_scale_freq_update: flag that enable/disable frequency change
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* @freq_table_sz: table size of frequencies supplied to devfreq
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* @freq_table: frequencies table supplied to devfreq
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* @curr_freq: current frequency
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* @polling_delay_ms: polling interval for status collection used by devfreq
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* @upthreshold: up-threshold supplied to ondemand governor
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* @downthreshold: down-threshold supplied to ondemand governor
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* @need_freq_change: flag indicating if a frequency change is required
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* @clk_scaling_in_progress: flag indicating if there's ongoing frequency change
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* @is_busy_started: flag indicating if a request is handled by the HW
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* @enable: flag indicating if the clock scaling logic is enabled for this host
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*/
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struct mmc_devfeq_clk_scaling {
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spinlock_t lock;
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struct devfreq *devfreq;
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struct devfreq_dev_profile devfreq_profile;
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struct devfreq_simple_ondemand_data ondemand_gov_data;
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enum mmc_load state;
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ktime_t start_busy;
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ktime_t measure_interval_start;
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atomic_t devfreq_abort;
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u32 skip_clk_scale_freq_update;
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int freq_table_sz;
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u32 *freq_table;
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unsigned long total_busy_time_us;
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unsigned long target_freq;
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unsigned long curr_freq;
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unsigned long polling_delay_ms;
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unsigned int upthreshold;
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unsigned int downthreshold;
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unsigned int lower_bus_speed_mode;
|
|
|
|
#define MMC_SCALING_LOWER_DDR52_MODE 1
|
|
|
|
bool need_freq_change;
|
|
|
|
bool clk_scaling_in_progress;
|
|
|
|
bool is_busy_started;
|
|
|
|
bool enable;
|
2024-09-09 08:52:07 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
struct mmc_host {
|
|
|
|
struct device *parent;
|
|
|
|
struct device class_dev;
|
2024-09-09 08:57:42 +00:00
|
|
|
struct mmc_devfeq_clk_scaling clk_scaling;
|
2024-09-09 08:52:07 +00:00
|
|
|
int index;
|
|
|
|
const struct mmc_host_ops *ops;
|
2024-09-09 08:57:42 +00:00
|
|
|
const struct mmc_cmdq_host_ops *cmdq_ops;
|
2024-09-09 08:52:07 +00:00
|
|
|
unsigned int f_min;
|
|
|
|
unsigned int f_max;
|
|
|
|
unsigned int f_init;
|
|
|
|
u32 ocr_avail;
|
|
|
|
u32 ocr_avail_sdio; /* SDIO-specific OCR */
|
|
|
|
u32 ocr_avail_sd; /* SD-specific OCR */
|
|
|
|
u32 ocr_avail_mmc; /* MMC-specific OCR */
|
|
|
|
struct notifier_block pm_notify;
|
2024-09-09 08:57:42 +00:00
|
|
|
u32 max_current_330;
|
|
|
|
u32 max_current_300;
|
|
|
|
u32 max_current_180;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
|
|
|
|
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
|
|
|
|
#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
|
|
|
|
#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
|
|
|
|
#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
|
|
|
|
#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
|
|
|
|
#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
|
|
|
|
#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
|
|
|
|
#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
|
|
|
|
#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
|
|
|
|
#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
|
|
|
|
#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
|
|
|
|
#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
|
|
|
|
#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
|
|
|
|
#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
|
|
|
|
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
|
|
|
|
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
u32 caps; /* Host capabilities */
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */
|
|
|
|
#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */
|
|
|
|
#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */
|
|
|
|
#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */
|
|
|
|
#define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */
|
|
|
|
#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */
|
|
|
|
#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */
|
2024-09-09 08:57:42 +00:00
|
|
|
#define MMC_CAP_AGGRESSIVE_PM (1 << 7) /* Suspend (e)MMC/SD at idle */
|
2024-09-09 08:52:07 +00:00
|
|
|
#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */
|
|
|
|
#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */
|
|
|
|
#define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */
|
|
|
|
#define MMC_CAP_1_8V_DDR (1 << 11) /* can support */
|
|
|
|
/* DDR mode at 1.8V */
|
|
|
|
#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */
|
|
|
|
/* DDR mode at 1.2V */
|
|
|
|
#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */
|
|
|
|
#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */
|
|
|
|
#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */
|
|
|
|
#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */
|
|
|
|
#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */
|
|
|
|
#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */
|
|
|
|
#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */
|
2024-09-09 08:57:42 +00:00
|
|
|
#define MMC_CAP_RUNTIME_RESUME (1 << 20) /* Resume at runtime_resume. */
|
2024-09-09 08:52:07 +00:00
|
|
|
#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
|
|
|
|
#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
|
|
|
|
#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */
|
|
|
|
#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */
|
|
|
|
#define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
u32 caps2; /* More host capabilities */
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
#define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */
|
2024-09-09 08:57:42 +00:00
|
|
|
#define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */
|
2024-09-09 08:52:07 +00:00
|
|
|
#define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */
|
|
|
|
#define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */
|
|
|
|
#define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \
|
|
|
|
MMC_CAP2_HS200_1_2V_SDR)
|
|
|
|
#define MMC_CAP2_HC_ERASE_SZ (1 << 9) /* High-capacity erase size */
|
2024-09-09 08:57:42 +00:00
|
|
|
#define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */
|
|
|
|
#define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */
|
2024-09-09 08:52:07 +00:00
|
|
|
#define MMC_CAP2_PACKED_RD (1 << 12) /* Allow packed read */
|
|
|
|
#define MMC_CAP2_PACKED_WR (1 << 13) /* Allow packed write */
|
|
|
|
#define MMC_CAP2_PACKED_CMD (MMC_CAP2_PACKED_RD | \
|
2024-09-09 08:57:42 +00:00
|
|
|
MMC_CAP2_PACKED_WR)
|
|
|
|
#define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */
|
|
|
|
#define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */
|
|
|
|
#define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */
|
|
|
|
#define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \
|
|
|
|
MMC_CAP2_HS400_1_2V)
|
|
|
|
#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
|
|
|
|
#define MMC_CAP2_PACKED_WR_CONTROL (1 << 18) /* Allow write packing control */
|
|
|
|
#define MMC_CAP2_CLK_SCALE (1 << 19) /* Allow dynamic clk scaling */
|
2024-09-09 08:52:07 +00:00
|
|
|
/* Allows Asynchronous SDIO irq while card is in 4-bit mode */
|
|
|
|
#define MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE (1 << 20)
|
2024-09-09 08:57:42 +00:00
|
|
|
/* Some hosts need additional tuning */
|
|
|
|
#define MMC_CAP2_HS400_POST_TUNING (1 << 21)
|
|
|
|
#define MMC_CAP2_NONHOTPLUG (1 << 25) /*Don't support hotplug*/
|
|
|
|
#define MMC_CAP2_CMD_QUEUE (1 << 26) /* support eMMC command queue */
|
|
|
|
#define MMC_CAP2_SANITIZE (1 << 27) /* Support Sanitize */
|
|
|
|
#define MMC_CAP2_SLEEP_AWAKE (1 << 28) /* Use Sleep/Awake (CMD5) */
|
|
|
|
/* use max discard ignoring max_busy_timeout parameter */
|
|
|
|
#define MMC_CAP2_MAX_DISCARD_SIZE (1 << 29)
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
mmc_pm_flag_t pm_caps; /* supported pm features */
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
#ifdef CONFIG_MMC_CLKGATE
|
2024-09-09 08:52:07 +00:00
|
|
|
int clk_requests; /* internal reference counter */
|
|
|
|
unsigned int clk_delay; /* number of MCI clk hold cycles */
|
|
|
|
bool clk_gated; /* clock gated */
|
|
|
|
struct delayed_work clk_gate_work; /* delayed clock gate */
|
|
|
|
unsigned int clk_old; /* old clock value cache */
|
|
|
|
spinlock_t clk_lock; /* lock for clk fields */
|
|
|
|
struct mutex clk_gate_mutex; /* mutex for clock gating */
|
|
|
|
struct device_attribute clkgate_delay_attr;
|
|
|
|
unsigned long clkgate_delay;
|
2024-09-09 08:57:42 +00:00
|
|
|
#endif
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
/* host specific block data */
|
|
|
|
unsigned int max_seg_size; /* see blk_queue_max_segment_size */
|
|
|
|
unsigned short max_segs; /* see blk_queue_max_segments */
|
|
|
|
unsigned short unused;
|
|
|
|
unsigned int max_req_size; /* maximum number of bytes in one req */
|
|
|
|
unsigned int max_blk_size; /* maximum size of one mmc block */
|
|
|
|
unsigned int max_blk_count; /* maximum number of blocks in one req */
|
2024-09-09 08:57:42 +00:00
|
|
|
unsigned int max_busy_timeout; /* max busy timeout in ms */
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
/* private data */
|
|
|
|
spinlock_t lock; /* lock for claim and bus ops */
|
|
|
|
|
|
|
|
struct mmc_ios ios; /* current io bus settings */
|
2024-09-09 08:57:42 +00:00
|
|
|
struct mmc_ios cached_ios;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
/* group bitfields together to minimize padding */
|
|
|
|
unsigned int use_spi_crc:1;
|
|
|
|
unsigned int claimed:1; /* host exclusively claimed */
|
|
|
|
unsigned int bus_dead:1; /* bus has been released */
|
|
|
|
#ifdef CONFIG_MMC_DEBUG
|
|
|
|
unsigned int removed:1; /* host is being removed */
|
|
|
|
#endif
|
|
|
|
|
|
|
|
int rescan_disable; /* disable card detection */
|
2024-09-09 08:57:42 +00:00
|
|
|
int rescan_entered; /* used with nonremovable devices */
|
|
|
|
|
|
|
|
bool trigger_card_event; /* card_event necessary */
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
struct mmc_card *card; /* device attached to this host */
|
|
|
|
|
|
|
|
wait_queue_head_t wq;
|
|
|
|
struct task_struct *claimer; /* task that has host claimed */
|
|
|
|
struct task_struct *suspend_task;
|
|
|
|
int claim_cnt; /* "claim" nesting count */
|
|
|
|
|
|
|
|
struct delayed_work detect;
|
|
|
|
int detect_change; /* card detect flag */
|
2024-09-09 08:57:42 +00:00
|
|
|
struct mmc_slot slot;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
const struct mmc_bus_ops *bus_ops; /* current bus driver */
|
|
|
|
unsigned int bus_refs; /* reference counter */
|
|
|
|
|
|
|
|
unsigned int sdio_irqs;
|
|
|
|
struct task_struct *sdio_irq_thread;
|
|
|
|
bool sdio_irq_pending;
|
|
|
|
atomic_t sdio_irq_thread_abort;
|
|
|
|
|
|
|
|
mmc_pm_flag_t pm_flags; /* requested pm features */
|
|
|
|
|
|
|
|
struct led_trigger *led; /* activity led */
|
|
|
|
|
|
|
|
#ifdef CONFIG_REGULATOR
|
|
|
|
bool regulator_enabled; /* regulator state */
|
|
|
|
#endif
|
2024-09-09 08:57:42 +00:00
|
|
|
struct mmc_supply supply;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
struct dentry *debugfs_root;
|
|
|
|
|
|
|
|
struct mmc_async_req *areq; /* active async req */
|
|
|
|
struct mmc_context_info context_info; /* async synchronization info */
|
|
|
|
|
|
|
|
#ifdef CONFIG_FAIL_MMC_REQUEST
|
|
|
|
struct fault_attr fail_mmc_request;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
unsigned int actual_clock; /* Actual HC clock rate */
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
unsigned int slotno; /* used for sdio acpi binding */
|
|
|
|
|
|
|
|
int dsr_req; /* DSR value is valid */
|
|
|
|
u32 dsr; /* optional driver stage (DSR) value */
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
#ifdef CONFIG_MMC_EMBEDDED_SDIO
|
|
|
|
struct {
|
|
|
|
struct sdio_cis *cis;
|
|
|
|
struct sdio_cccr *cccr;
|
|
|
|
struct sdio_embedded_func *funcs;
|
|
|
|
int num_funcs;
|
|
|
|
} embedded_sdio_data;
|
|
|
|
#endif
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
/*
|
|
|
|
* Set to 1 to just stop the SDCLK to the card without
|
|
|
|
* actually disabling the clock from it's source.
|
|
|
|
*/
|
|
|
|
bool card_clock_off;
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
#ifdef CONFIG_MMC_PERF_PROFILING
|
|
|
|
struct {
|
|
|
|
|
|
|
|
unsigned long rbytes_drv; /* Rd bytes MMC Host */
|
|
|
|
unsigned long wbytes_drv; /* Wr bytes MMC Host */
|
|
|
|
ktime_t rtime_drv; /* Rd time MMC Host */
|
|
|
|
ktime_t wtime_drv; /* Wr time MMC Host */
|
|
|
|
ktime_t start;
|
|
|
|
} perf;
|
|
|
|
bool perf_enable;
|
|
|
|
#endif
|
2024-09-09 08:57:42 +00:00
|
|
|
enum dev_state dev_status;
|
|
|
|
bool wakeup_on_idle;
|
|
|
|
struct mmc_cmdq_context_info cmdq_ctx;
|
|
|
|
int num_cq_slots;
|
|
|
|
int dcmd_cq_slot;
|
|
|
|
u32 cmdq_thist_enabled;
|
|
|
|
/*
|
|
|
|
* several cmdq supporting host controllers are extensions
|
|
|
|
* of legacy controllers. This variable can be used to store
|
|
|
|
* a reference to the cmdq extension of the existing host
|
|
|
|
* controller.
|
|
|
|
*/
|
|
|
|
void *cmdq_private;
|
|
|
|
struct mmc_request *err_mrq;
|
2024-09-09 08:52:07 +00:00
|
|
|
unsigned long private[0] ____cacheline_aligned;
|
|
|
|
};
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
struct mmc_host *mmc_alloc_host(int extra, struct device *);
|
2024-09-09 08:52:07 +00:00
|
|
|
extern bool mmc_host_may_gate_card(struct mmc_card *);
|
2024-09-09 08:57:42 +00:00
|
|
|
int mmc_add_host(struct mmc_host *);
|
|
|
|
void mmc_remove_host(struct mmc_host *);
|
|
|
|
void mmc_free_host(struct mmc_host *);
|
|
|
|
int mmc_of_parse(struct mmc_host *host);
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_MMC_EMBEDDED_SDIO
|
|
|
|
extern void mmc_set_embedded_sdio_data(struct mmc_host *host,
|
|
|
|
struct sdio_cis *cis,
|
|
|
|
struct sdio_cccr *cccr,
|
|
|
|
struct sdio_embedded_func *funcs,
|
|
|
|
int num_funcs);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static inline void *mmc_priv(struct mmc_host *host)
|
|
|
|
{
|
|
|
|
return (void *)host->private;
|
|
|
|
}
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
static inline void *mmc_cmdq_private(struct mmc_host *host)
|
|
|
|
{
|
|
|
|
return host->cmdq_private;
|
|
|
|
}
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
#define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI)
|
|
|
|
|
|
|
|
#define mmc_dev(x) ((x)->parent)
|
|
|
|
#define mmc_classdev(x) (&(x)->class_dev)
|
|
|
|
#define mmc_hostname(x) (dev_name(&(x)->class_dev))
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
int mmc_power_save_host(struct mmc_host *host);
|
|
|
|
int mmc_power_restore_host(struct mmc_host *host);
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
void mmc_detect_change(struct mmc_host *, unsigned long delay);
|
|
|
|
void mmc_request_done(struct mmc_host *, struct mmc_request *);
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2024-09-09 08:52:07 +00:00
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static inline void mmc_signal_sdio_irq(struct mmc_host *host)
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{
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host->ops->enable_sdio_irq(host, 0);
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host->sdio_irq_pending = true;
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wake_up_process(host->sdio_irq_thread);
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}
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2024-09-09 08:57:42 +00:00
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void sdio_run_irqs(struct mmc_host *host);
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2024-09-09 08:52:07 +00:00
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#ifdef CONFIG_REGULATOR
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int mmc_regulator_get_ocrmask(struct regulator *supply);
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int mmc_regulator_set_ocr(struct mmc_host *mmc,
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struct regulator *supply,
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unsigned short vdd_bit);
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#else
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static inline int mmc_regulator_get_ocrmask(struct regulator *supply)
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{
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return 0;
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}
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static inline int mmc_regulator_set_ocr(struct mmc_host *mmc,
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struct regulator *supply,
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unsigned short vdd_bit)
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{
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return 0;
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}
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#endif
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2024-09-09 08:57:42 +00:00
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int mmc_regulator_get_supply(struct mmc_host *mmc);
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2024-09-09 08:52:07 +00:00
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int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *);
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static inline int mmc_card_is_removable(struct mmc_host *host)
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{
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2024-09-09 08:57:42 +00:00
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return !(host->caps & MMC_CAP_NONREMOVABLE);
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2024-09-09 08:52:07 +00:00
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}
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static inline int mmc_card_keep_power(struct mmc_host *host)
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{
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return host->pm_flags & MMC_PM_KEEP_POWER;
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}
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static inline int mmc_card_wake_sdio_irq(struct mmc_host *host)
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{
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return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ;
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}
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static inline int mmc_host_cmd23(struct mmc_host *host)
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{
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return host->caps & MMC_CAP_CMD23;
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}
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static inline int mmc_boot_partition_access(struct mmc_host *host)
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{
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return !(host->caps2 & MMC_CAP2_BOOTPART_NOACC);
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}
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2024-09-09 08:57:42 +00:00
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static inline bool mmc_card_and_host_support_async_int(struct mmc_host *host)
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{
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return ((host->caps2 & MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE) &&
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(host->card->cccr.async_intr_sup));
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}
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|
2024-09-09 08:52:07 +00:00
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static inline int mmc_host_uhs(struct mmc_host *host)
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{
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return host->caps &
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(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
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MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
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MMC_CAP_UHS_DDR50);
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}
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|
2024-09-09 08:57:42 +00:00
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static inline int mmc_host_packed_wr(struct mmc_host *host)
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{
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return host->caps2 & MMC_CAP2_PACKED_WR;
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}
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static inline void mmc_host_set_halt(struct mmc_host *host)
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{
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set_bit(CMDQ_STATE_HALT, &host->cmdq_ctx.curr_state);
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}
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static inline void mmc_host_clr_halt(struct mmc_host *host)
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{
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clear_bit(CMDQ_STATE_HALT, &host->cmdq_ctx.curr_state);
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}
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static inline int mmc_host_halt(struct mmc_host *host)
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{
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|
return test_bit(CMDQ_STATE_HALT, &host->cmdq_ctx.curr_state);
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}
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static inline void mmc_host_set_cq_disable(struct mmc_host *host)
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|
{
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|
set_bit(CMDQ_STATE_CQ_DISABLE, &host->cmdq_ctx.curr_state);
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}
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static inline void mmc_host_clr_cq_disable(struct mmc_host *host)
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|
|
{
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|
clear_bit(CMDQ_STATE_CQ_DISABLE, &host->cmdq_ctx.curr_state);
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|
}
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static inline int mmc_host_cq_disable(struct mmc_host *host)
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|
|
{
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|
return test_bit(CMDQ_STATE_CQ_DISABLE, &host->cmdq_ctx.curr_state);
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}
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|
2024-09-09 08:52:07 +00:00
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#ifdef CONFIG_MMC_CLKGATE
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|
|
void mmc_host_clk_hold(struct mmc_host *host);
|
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|
|
void mmc_host_clk_release(struct mmc_host *host);
|
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|
|
unsigned int mmc_host_clk_rate(struct mmc_host *host);
|
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|
|
|
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|
#else
|
|
|
|
static inline void mmc_host_clk_hold(struct mmc_host *host)
|
|
|
|
{
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|
|
|
}
|
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|
static inline void mmc_host_clk_release(struct mmc_host *host)
|
|
|
|
{
|
|
|
|
}
|
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|
|
static inline unsigned int mmc_host_clk_rate(struct mmc_host *host)
|
|
|
|
{
|
|
|
|
return host->ios.clock;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
static inline int mmc_card_hs(struct mmc_card *card)
|
|
|
|
{
|
|
|
|
return card->host->ios.timing == MMC_TIMING_SD_HS ||
|
|
|
|
card->host->ios.timing == MMC_TIMING_MMC_HS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int mmc_card_uhs(struct mmc_card *card)
|
|
|
|
{
|
|
|
|
return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 &&
|
|
|
|
card->host->ios.timing <= MMC_TIMING_UHS_DDR50;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool mmc_card_hs200(struct mmc_card *card)
|
|
|
|
{
|
|
|
|
return card->host->ios.timing == MMC_TIMING_MMC_HS200;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool mmc_card_ddr52(struct mmc_card *card)
|
|
|
|
{
|
|
|
|
return card->host->ios.timing == MMC_TIMING_MMC_DDR52;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool mmc_card_hs400(struct mmc_card *card)
|
2024-09-09 08:52:07 +00:00
|
|
|
{
|
2024-09-09 08:57:42 +00:00
|
|
|
return card->host->ios.timing == MMC_TIMING_MMC_HS400;
|
2024-09-09 08:52:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* LINUX_MMC_HOST_H */
|