2024-09-09 08:52:07 +00:00
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#ifndef __LINUX_CACHE_H
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#define __LINUX_CACHE_H
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2024-09-09 08:57:42 +00:00
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#include <uapi/linux/kernel.h>
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2024-09-09 08:52:07 +00:00
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#include <asm/cache.h>
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#ifndef L1_CACHE_ALIGN
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2024-09-09 08:57:42 +00:00
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#define L1_CACHE_ALIGN(x) __ALIGN_KERNEL(x, L1_CACHE_BYTES)
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2024-09-09 08:52:07 +00:00
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#endif
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#ifndef SMP_CACHE_BYTES
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#endif
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#ifndef __read_mostly
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#define __read_mostly
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#endif
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#ifndef ____cacheline_aligned
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#define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
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#endif
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#ifndef ____cacheline_aligned_in_smp
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#ifdef CONFIG_SMP
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#define ____cacheline_aligned_in_smp ____cacheline_aligned
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#else
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#define ____cacheline_aligned_in_smp
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#endif /* CONFIG_SMP */
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#endif
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#ifndef __cacheline_aligned
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#define __cacheline_aligned \
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__attribute__((__aligned__(SMP_CACHE_BYTES), \
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__section__(".data..cacheline_aligned")))
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#endif /* __cacheline_aligned */
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#ifndef __cacheline_aligned_in_smp
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#ifdef CONFIG_SMP
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#define __cacheline_aligned_in_smp __cacheline_aligned
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#else
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#define __cacheline_aligned_in_smp
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#endif /* CONFIG_SMP */
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#endif
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/*
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* The maximum alignment needed for some critical structures
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* These could be inter-node cacheline sizes/L3 cacheline
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* size etc. Define this in asm/cache.h for your arch
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*/
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#ifndef INTERNODE_CACHE_SHIFT
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#define INTERNODE_CACHE_SHIFT L1_CACHE_SHIFT
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#endif
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#if !defined(____cacheline_internodealigned_in_smp)
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#if defined(CONFIG_SMP)
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#define ____cacheline_internodealigned_in_smp \
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__attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT))))
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#else
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#define ____cacheline_internodealigned_in_smp
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#endif
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#endif
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#ifndef CONFIG_ARCH_HAS_CACHE_LINE_SIZE
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#define cache_line_size() L1_CACHE_BYTES
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#endif
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#endif /* __LINUX_CACHE_H */
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