2024-09-09 08:52:07 +00:00
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/* vi: ts=8 sw=8
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*
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* TI 3410/5052 USB Serial Driver Header
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*
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* Copyright (C) 2004 Texas Instruments
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*
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* This driver is based on the Linux io_ti driver, which is
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* Copyright (C) 2000-2002 Inside Out Networks
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* Copyright (C) 2001-2002 Greg Kroah-Hartman
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* For questions or problems with this driver, contact Texas Instruments
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* technical support, or Al Borchers <alborchers@steinerpoint.com>, or
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* Peter Berger <pberger@brimson.com>.
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*/
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#ifndef _TI_3410_5052_H_
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#define _TI_3410_5052_H_
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/* Configuration ids */
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#define TI_BOOT_CONFIG 1
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#define TI_ACTIVE_CONFIG 2
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/* Vendor and product ids */
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#define TI_VENDOR_ID 0x0451
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#define IBM_VENDOR_ID 0x04b3
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#define TI_3410_PRODUCT_ID 0x3410
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#define IBM_4543_PRODUCT_ID 0x4543
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#define IBM_454B_PRODUCT_ID 0x454b
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#define IBM_454C_PRODUCT_ID 0x454c
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#define TI_3410_EZ430_ID 0xF430 /* TI ez430 development tool */
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#define TI_5052_BOOT_PRODUCT_ID 0x5052 /* no EEPROM, no firmware */
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#define TI_5152_BOOT_PRODUCT_ID 0x5152 /* no EEPROM, no firmware */
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#define TI_5052_EEPROM_PRODUCT_ID 0x505A /* EEPROM, no firmware */
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#define TI_5052_FIRMWARE_PRODUCT_ID 0x505F /* firmware is running */
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#define FRI2_PRODUCT_ID 0x5053 /* Fish River Island II */
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/* Multi-Tech vendor and product ids */
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#define MTS_VENDOR_ID 0x06E0
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#define MTS_GSM_NO_FW_PRODUCT_ID 0xF108
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#define MTS_CDMA_NO_FW_PRODUCT_ID 0xF109
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#define MTS_CDMA_PRODUCT_ID 0xF110
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#define MTS_GSM_PRODUCT_ID 0xF111
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#define MTS_EDGE_PRODUCT_ID 0xF112
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#define MTS_MT9234MU_PRODUCT_ID 0xF114
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#define MTS_MT9234ZBA_PRODUCT_ID 0xF115
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#define MTS_MT9234ZBAOLD_PRODUCT_ID 0x0319
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/* Abbott Diabetics vendor and product ids */
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#define ABBOTT_VENDOR_ID 0x1a61
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#define ABBOTT_STEREO_PLUG_ID 0x3410
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#define ABBOTT_PRODUCT_ID ABBOTT_STEREO_PLUG_ID
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#define ABBOTT_STRIP_PORT_ID 0x3420
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/* Commands */
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#define TI_GET_VERSION 0x01
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#define TI_GET_PORT_STATUS 0x02
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#define TI_GET_PORT_DEV_INFO 0x03
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#define TI_GET_CONFIG 0x04
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#define TI_SET_CONFIG 0x05
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#define TI_OPEN_PORT 0x06
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#define TI_CLOSE_PORT 0x07
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#define TI_START_PORT 0x08
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#define TI_STOP_PORT 0x09
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#define TI_TEST_PORT 0x0A
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#define TI_PURGE_PORT 0x0B
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#define TI_RESET_EXT_DEVICE 0x0C
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#define TI_WRITE_DATA 0x80
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#define TI_READ_DATA 0x81
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#define TI_REQ_TYPE_CLASS 0x82
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/* Module identifiers */
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#define TI_I2C_PORT 0x01
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#define TI_IEEE1284_PORT 0x02
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#define TI_UART1_PORT 0x03
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#define TI_UART2_PORT 0x04
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#define TI_RAM_PORT 0x05
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/* Modem status */
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#define TI_MSR_DELTA_CTS 0x01
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#define TI_MSR_DELTA_DSR 0x02
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#define TI_MSR_DELTA_RI 0x04
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#define TI_MSR_DELTA_CD 0x08
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#define TI_MSR_CTS 0x10
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#define TI_MSR_DSR 0x20
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#define TI_MSR_RI 0x40
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#define TI_MSR_CD 0x80
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#define TI_MSR_DELTA_MASK 0x0F
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#define TI_MSR_MASK 0xF0
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/* Line status */
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#define TI_LSR_OVERRUN_ERROR 0x01
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#define TI_LSR_PARITY_ERROR 0x02
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#define TI_LSR_FRAMING_ERROR 0x04
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#define TI_LSR_BREAK 0x08
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#define TI_LSR_ERROR 0x0F
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#define TI_LSR_RX_FULL 0x10
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#define TI_LSR_TX_EMPTY 0x20
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/* Line control */
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#define TI_LCR_BREAK 0x40
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/* Modem control */
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#define TI_MCR_LOOP 0x04
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#define TI_MCR_DTR 0x10
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#define TI_MCR_RTS 0x20
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/* Mask settings */
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#define TI_UART_ENABLE_RTS_IN 0x0001
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#define TI_UART_DISABLE_RTS 0x0002
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#define TI_UART_ENABLE_PARITY_CHECKING 0x0008
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#define TI_UART_ENABLE_DSR_OUT 0x0010
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#define TI_UART_ENABLE_CTS_OUT 0x0020
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#define TI_UART_ENABLE_X_OUT 0x0040
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#define TI_UART_ENABLE_XA_OUT 0x0080
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#define TI_UART_ENABLE_X_IN 0x0100
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#define TI_UART_ENABLE_DTR_IN 0x0800
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#define TI_UART_DISABLE_DTR 0x1000
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#define TI_UART_ENABLE_MS_INTS 0x2000
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#define TI_UART_ENABLE_AUTO_START_DMA 0x4000
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/* Parity */
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#define TI_UART_NO_PARITY 0x00
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#define TI_UART_ODD_PARITY 0x01
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#define TI_UART_EVEN_PARITY 0x02
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#define TI_UART_MARK_PARITY 0x03
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#define TI_UART_SPACE_PARITY 0x04
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/* Stop bits */
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#define TI_UART_1_STOP_BITS 0x00
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#define TI_UART_1_5_STOP_BITS 0x01
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#define TI_UART_2_STOP_BITS 0x02
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/* Bits per character */
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#define TI_UART_5_DATA_BITS 0x00
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#define TI_UART_6_DATA_BITS 0x01
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#define TI_UART_7_DATA_BITS 0x02
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#define TI_UART_8_DATA_BITS 0x03
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/* 232/485 modes */
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#define TI_UART_232 0x00
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#define TI_UART_485_RECEIVER_DISABLED 0x01
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#define TI_UART_485_RECEIVER_ENABLED 0x02
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/* Pipe transfer mode and timeout */
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#define TI_PIPE_MODE_CONTINOUS 0x01
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#define TI_PIPE_MODE_MASK 0x03
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#define TI_PIPE_TIMEOUT_MASK 0x7C
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#define TI_PIPE_TIMEOUT_ENABLE 0x80
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/* Config struct */
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struct ti_uart_config {
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__u16 wBaudRate;
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__u16 wFlags;
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__u8 bDataBits;
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__u8 bParity;
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__u8 bStopBits;
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char cXon;
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char cXoff;
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__u8 bUartMode;
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} __attribute__((packed));
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/* Get port status */
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struct ti_port_status {
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__u8 bCmdCode;
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__u8 bModuleId;
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__u8 bErrorCode;
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__u8 bMSR;
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__u8 bLSR;
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} __attribute__((packed));
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/* Purge modes */
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#define TI_PURGE_OUTPUT 0x00
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#define TI_PURGE_INPUT 0x80
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/* Read/Write data */
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#define TI_RW_DATA_ADDR_SFR 0x10
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#define TI_RW_DATA_ADDR_IDATA 0x20
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#define TI_RW_DATA_ADDR_XDATA 0x30
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#define TI_RW_DATA_ADDR_CODE 0x40
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#define TI_RW_DATA_ADDR_GPIO 0x50
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#define TI_RW_DATA_ADDR_I2C 0x60
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#define TI_RW_DATA_ADDR_FLASH 0x70
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#define TI_RW_DATA_ADDR_DSP 0x80
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#define TI_RW_DATA_UNSPECIFIED 0x00
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#define TI_RW_DATA_BYTE 0x01
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#define TI_RW_DATA_WORD 0x02
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#define TI_RW_DATA_DOUBLE_WORD 0x04
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struct ti_write_data_bytes {
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__u8 bAddrType;
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__u8 bDataType;
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__u8 bDataCounter;
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__be16 wBaseAddrHi;
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__be16 wBaseAddrLo;
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__u8 bData[0];
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} __attribute__((packed));
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struct ti_read_data_request {
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__u8 bAddrType;
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__u8 bDataType;
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__u8 bDataCounter;
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__be16 wBaseAddrHi;
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__be16 wBaseAddrLo;
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} __attribute__((packed));
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struct ti_read_data_bytes {
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__u8 bCmdCode;
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__u8 bModuleId;
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__u8 bErrorCode;
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__u8 bData[0];
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} __attribute__((packed));
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/* Interrupt struct */
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struct ti_interrupt {
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__u8 bICode;
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__u8 bIInfo;
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} __attribute__((packed));
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/* Interrupt codes */
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#define TI_GET_PORT_FROM_CODE(c) (((c) >> 4) - 3)
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#define TI_GET_FUNC_FROM_CODE(c) ((c) & 0x0f)
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#define TI_CODE_HARDWARE_ERROR 0xFF
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#define TI_CODE_DATA_ERROR 0x03
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#define TI_CODE_MODEM_STATUS 0x04
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/* Download firmware max packet size */
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#define TI_DOWNLOAD_MAX_PACKET_SIZE 64
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/* Firmware image header */
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struct ti_firmware_header {
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__le16 wLength;
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__u8 bCheckSum;
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} __attribute__((packed));
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/* UART addresses */
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#define TI_UART1_BASE_ADDR 0xFFA0 /* UART 1 base address */
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#define TI_UART2_BASE_ADDR 0xFFB0 /* UART 2 base address */
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#define TI_UART_OFFSET_LCR 0x0002 /* UART MCR register offset */
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#define TI_UART_OFFSET_MCR 0x0004 /* UART MCR register offset */
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#endif /* _TI_3410_5052_H_ */
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