2024-09-09 08:52:07 +00:00
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/*
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* QLogic iSCSI HBA Driver
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2024-09-09 08:57:42 +00:00
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* Copyright (c) 2003-2012 QLogic Corporation
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2024-09-09 08:52:07 +00:00
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*
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* See LICENSE.qla4xxx for copyright and licensing details.
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*/
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#include "ql4_def.h"
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#include "ql4_glbl.h"
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#include "ql4_dbg.h"
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#include "ql4_inline.h"
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void qla4xxx_dump_buffer(void *b, uint32_t size)
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{
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uint32_t cnt;
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uint8_t *c = b;
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printk(" 0 1 2 3 4 5 6 7 8 9 Ah Bh Ch Dh Eh "
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"Fh\n");
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printk("------------------------------------------------------------"
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"--\n");
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for (cnt = 0; cnt < size; c++) {
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printk("%02x", *c);
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if (!(++cnt % 16))
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printk("\n");
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else
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printk(" ");
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}
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printk(KERN_INFO "\n");
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}
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void qla4xxx_dump_registers(struct scsi_qla_host *ha)
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{
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uint8_t i;
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if (is_qla8022(ha)) {
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for (i = 1; i < MBOX_REG_COUNT; i++)
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printk(KERN_INFO "mailbox[%d] = 0x%08X\n",
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2024-09-09 08:57:42 +00:00
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i, readl(&ha->qla4_82xx_reg->mailbox_in[i]));
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2024-09-09 08:52:07 +00:00
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return;
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}
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for (i = 0; i < MBOX_REG_COUNT; i++) {
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printk(KERN_INFO "0x%02X mailbox[%d] = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, mailbox[i]), i,
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readw(&ha->reg->mailbox[i]));
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}
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printk(KERN_INFO "0x%02X flash_address = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, flash_address),
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readw(&ha->reg->flash_address));
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printk(KERN_INFO "0x%02X flash_data = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, flash_data),
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readw(&ha->reg->flash_data));
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printk(KERN_INFO "0x%02X ctrl_status = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, ctrl_status),
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readw(&ha->reg->ctrl_status));
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if (is_qla4010(ha)) {
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printk(KERN_INFO "0x%02X nvram = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u1.isp4010.nvram),
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readw(&ha->reg->u1.isp4010.nvram));
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} else if (is_qla4022(ha) | is_qla4032(ha)) {
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printk(KERN_INFO "0x%02X intr_mask = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u1.isp4022.intr_mask),
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readw(&ha->reg->u1.isp4022.intr_mask));
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printk(KERN_INFO "0x%02X nvram = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u1.isp4022.nvram),
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readw(&ha->reg->u1.isp4022.nvram));
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printk(KERN_INFO "0x%02X semaphore = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u1.isp4022.semaphore),
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readw(&ha->reg->u1.isp4022.semaphore));
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}
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printk(KERN_INFO "0x%02X req_q_in = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, req_q_in),
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readw(&ha->reg->req_q_in));
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printk(KERN_INFO "0x%02X rsp_q_out = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, rsp_q_out),
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readw(&ha->reg->rsp_q_out));
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if (is_qla4010(ha)) {
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printk(KERN_INFO "0x%02X ext_hw_conf = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u2.isp4010.ext_hw_conf),
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readw(&ha->reg->u2.isp4010.ext_hw_conf));
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printk(KERN_INFO "0x%02X port_ctrl = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u2.isp4010.port_ctrl),
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readw(&ha->reg->u2.isp4010.port_ctrl));
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printk(KERN_INFO "0x%02X port_status = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u2.isp4010.port_status),
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readw(&ha->reg->u2.isp4010.port_status));
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printk(KERN_INFO "0x%02X req_q_out = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u2.isp4010.req_q_out),
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readw(&ha->reg->u2.isp4010.req_q_out));
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printk(KERN_INFO "0x%02X gp_out = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_out),
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readw(&ha->reg->u2.isp4010.gp_out));
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printk(KERN_INFO "0x%02X gp_in = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_in),
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readw(&ha->reg->u2.isp4010.gp_in));
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printk(KERN_INFO "0x%02X port_err_status = 0x%08X\n", (uint8_t)
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offsetof(struct isp_reg, u2.isp4010.port_err_status),
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readw(&ha->reg->u2.isp4010.port_err_status));
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} else if (is_qla4022(ha) | is_qla4032(ha)) {
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printk(KERN_INFO "Page 0 Registers:\n");
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printk(KERN_INFO "0x%02X ext_hw_conf = 0x%08X\n", (uint8_t)
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offsetof(struct isp_reg, u2.isp4022.p0.ext_hw_conf),
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readw(&ha->reg->u2.isp4022.p0.ext_hw_conf));
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printk(KERN_INFO "0x%02X port_ctrl = 0x%08X\n", (uint8_t)
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offsetof(struct isp_reg, u2.isp4022.p0.port_ctrl),
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readw(&ha->reg->u2.isp4022.p0.port_ctrl));
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printk(KERN_INFO "0x%02X port_status = 0x%08X\n", (uint8_t)
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offsetof(struct isp_reg, u2.isp4022.p0.port_status),
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readw(&ha->reg->u2.isp4022.p0.port_status));
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printk(KERN_INFO "0x%02X gp_out = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_out),
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readw(&ha->reg->u2.isp4022.p0.gp_out));
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printk(KERN_INFO "0x%02X gp_in = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_in),
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readw(&ha->reg->u2.isp4022.p0.gp_in));
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printk(KERN_INFO "0x%02X port_err_status = 0x%08X\n", (uint8_t)
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offsetof(struct isp_reg, u2.isp4022.p0.port_err_status),
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readw(&ha->reg->u2.isp4022.p0.port_err_status));
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printk(KERN_INFO "Page 1 Registers:\n");
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writel(HOST_MEM_CFG_PAGE & set_rmask(CSR_SCSI_PAGE_SELECT),
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&ha->reg->ctrl_status);
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printk(KERN_INFO "0x%02X req_q_out = 0x%08X\n",
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(uint8_t) offsetof(struct isp_reg, u2.isp4022.p1.req_q_out),
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readw(&ha->reg->u2.isp4022.p1.req_q_out));
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writel(PORT_CTRL_STAT_PAGE & set_rmask(CSR_SCSI_PAGE_SELECT),
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&ha->reg->ctrl_status);
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}
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}
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2024-09-09 08:57:42 +00:00
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void qla4_8xxx_dump_peg_reg(struct scsi_qla_host *ha)
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{
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uint32_t halt_status1, halt_status2;
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halt_status1 = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_HALT_STATUS1);
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halt_status2 = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_HALT_STATUS2);
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if (is_qla8022(ha)) {
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ql4_printk(KERN_INFO, ha,
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"scsi(%ld): %s, ISP%04x Dumping hw/fw registers:\n"
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" PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
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" PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
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" PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
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" PEG_NET_4_PC: 0x%x\n", ha->host_no, __func__,
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ha->pdev->device, halt_status1, halt_status2,
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qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c),
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qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c),
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qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c),
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qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c),
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qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c));
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} else if (is_qla8032(ha) || is_qla8042(ha)) {
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ql4_printk(KERN_INFO, ha,
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"scsi(%ld): %s, ISP%04x Dumping hw/fw registers:\n"
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" PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n",
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ha->host_no, __func__, ha->pdev->device,
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halt_status1, halt_status2);
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}
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}
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