404 lines
13 KiB
C
404 lines
13 KiB
C
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/*
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* This file is part of the Chelsio FCoE driver for Linux.
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*
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* Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "csio_hw.h"
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#include "csio_init.h"
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/*
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* Return the specified PCI-E Configuration Space register from our Physical
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* Function. We try first via a Firmware LDST Command since we prefer to let
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* the firmware own all of these registers, but if that fails we go for it
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* directly ourselves.
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*/
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static uint32_t
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csio_t4_read_pcie_cfg4(struct csio_hw *hw, int reg)
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{
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u32 val = 0;
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struct csio_mb *mbp;
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int rv;
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struct fw_ldst_cmd *ldst_cmd;
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mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
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if (!mbp) {
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CSIO_INC_STATS(hw, n_err_nomem);
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pci_read_config_dword(hw->pdev, reg, &val);
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return val;
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}
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csio_mb_ldst(hw, mbp, CSIO_MB_DEFAULT_TMO, reg);
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rv = csio_mb_issue(hw, mbp);
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/*
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* If the LDST Command suucceeded, exctract the returned register
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* value. Otherwise read it directly ourself.
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*/
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if (rv == 0) {
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ldst_cmd = (struct fw_ldst_cmd *)(mbp->mb);
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val = ntohl(ldst_cmd->u.pcie.data[0]);
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} else
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pci_read_config_dword(hw->pdev, reg, &val);
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mempool_free(mbp, hw->mb_mempool);
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return val;
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}
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static int
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csio_t4_set_mem_win(struct csio_hw *hw, uint32_t win)
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{
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u32 bar0;
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u32 mem_win_base;
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/*
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* Truncation intentional: we only read the bottom 32-bits of the
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* 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to
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* read BAR0 instead of using pci_resource_start() because we could be
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* operating from within a Virtual Machine which is trapping our
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* accesses to our Configuration Space and we need to set up the PCI-E
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* Memory Window decoders with the actual addresses which will be
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* coming across the PCI-E link.
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*/
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bar0 = csio_t4_read_pcie_cfg4(hw, PCI_BASE_ADDRESS_0);
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bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
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mem_win_base = bar0 + MEMWIN_BASE;
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/*
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* Set up memory window for accessing adapter memory ranges. (Read
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* back MA register to ensure that changes propagate before we attempt
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* to use the new values.)
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*/
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csio_wr_reg32(hw, mem_win_base | BIR(0) |
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WINDOW(ilog2(MEMWIN_APERTURE) - 10),
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PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
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csio_rd_reg32(hw,
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PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
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return 0;
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}
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/*
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* Interrupt handler for the PCIE module.
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*/
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static void
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csio_t4_pcie_intr_handler(struct csio_hw *hw)
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{
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static struct intr_info sysbus_intr_info[] = {
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{ RNPP, "RXNP array parity error", -1, 1 },
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{ RPCP, "RXPC array parity error", -1, 1 },
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{ RCIP, "RXCIF array parity error", -1, 1 },
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{ RCCP, "Rx completions control array parity error", -1, 1 },
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{ RFTP, "RXFT array parity error", -1, 1 },
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{ 0, NULL, 0, 0 }
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};
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static struct intr_info pcie_port_intr_info[] = {
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{ TPCP, "TXPC array parity error", -1, 1 },
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{ TNPP, "TXNP array parity error", -1, 1 },
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{ TFTP, "TXFT array parity error", -1, 1 },
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{ TCAP, "TXCA array parity error", -1, 1 },
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{ TCIP, "TXCIF array parity error", -1, 1 },
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{ RCAP, "RXCA array parity error", -1, 1 },
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{ OTDD, "outbound request TLP discarded", -1, 1 },
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{ RDPE, "Rx data parity error", -1, 1 },
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{ TDUE, "Tx uncorrectable data error", -1, 1 },
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{ 0, NULL, 0, 0 }
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};
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static struct intr_info pcie_intr_info[] = {
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{ MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
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{ MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
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{ MSIDATAPERR, "MSI data parity error", -1, 1 },
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{ MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
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{ MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
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{ MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
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{ MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
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{ PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
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{ PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
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{ TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
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{ CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
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{ CREQPERR, "PCI CMD channel request parity error", -1, 1 },
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{ CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
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{ DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
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{ DREQPERR, "PCI DMA channel request parity error", -1, 1 },
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{ DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
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{ HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
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{ HREQPERR, "PCI HMA channel request parity error", -1, 1 },
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{ HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
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{ CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
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{ FIDPERR, "PCI FID parity error", -1, 1 },
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{ INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
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{ MATAGPERR, "PCI MA tag parity error", -1, 1 },
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{ PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
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{ RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
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{ RXWRPERR, "PCI Rx write parity error", -1, 1 },
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{ RPLPERR, "PCI replay buffer parity error", -1, 1 },
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{ PCIESINT, "PCI core secondary fault", -1, 1 },
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{ PCIEPINT, "PCI core primary fault", -1, 1 },
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{ UNXSPLCPLERR, "PCI unexpected split completion error", -1,
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0 },
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{ 0, NULL, 0, 0 }
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};
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int fat;
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fat = csio_handle_intr_status(hw,
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PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
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sysbus_intr_info) +
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csio_handle_intr_status(hw,
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PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
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pcie_port_intr_info) +
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csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info);
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if (fat)
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csio_hw_fatal_err(hw);
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}
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/*
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* csio_t4_flash_cfg_addr - return the address of the flash configuration file
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* @hw: the HW module
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*
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* Return the address within the flash where the Firmware Configuration
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* File is stored.
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*/
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static unsigned int
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csio_t4_flash_cfg_addr(struct csio_hw *hw)
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{
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return FLASH_CFG_OFFSET;
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}
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/*
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* csio_t4_mc_read - read from MC through backdoor accesses
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* @hw: the hw module
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* @idx: not used for T4 adapter
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* @addr: address of first byte requested
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* @data: 64 bytes of data containing the requested address
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* @ecc: where to store the corresponding 64-bit ECC word
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*
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* Read 64 bytes of data from MC starting at a 64-byte-aligned address
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* that covers the requested address @addr. If @parity is not %NULL it
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* is assigned the 64-bit ECC word for the read data.
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*/
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static int
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csio_t4_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
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uint64_t *ecc)
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{
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int i;
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if (csio_rd_reg32(hw, MC_BIST_CMD) & START_BIST)
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return -EBUSY;
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csio_wr_reg32(hw, addr & ~0x3fU, MC_BIST_CMD_ADDR);
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csio_wr_reg32(hw, 64, MC_BIST_CMD_LEN);
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csio_wr_reg32(hw, 0xc, MC_BIST_DATA_PATTERN);
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csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST | BIST_CMD_GAP(1),
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MC_BIST_CMD);
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i = csio_hw_wait_op_done_val(hw, MC_BIST_CMD, START_BIST,
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0, 10, 1, NULL);
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if (i)
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return i;
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#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i)
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for (i = 15; i >= 0; i--)
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*data++ = htonl(csio_rd_reg32(hw, MC_DATA(i)));
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if (ecc)
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*ecc = csio_rd_reg64(hw, MC_DATA(16));
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#undef MC_DATA
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return 0;
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}
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/*
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* csio_t4_edc_read - read from EDC through backdoor accesses
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* @hw: the hw module
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* @idx: which EDC to access
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* @addr: address of first byte requested
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* @data: 64 bytes of data containing the requested address
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* @ecc: where to store the corresponding 64-bit ECC word
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*
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* Read 64 bytes of data from EDC starting at a 64-byte-aligned address
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* that covers the requested address @addr. If @parity is not %NULL it
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* is assigned the 64-bit ECC word for the read data.
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*/
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static int
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csio_t4_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
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uint64_t *ecc)
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{
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int i;
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idx *= EDC_STRIDE;
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if (csio_rd_reg32(hw, EDC_BIST_CMD + idx) & START_BIST)
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return -EBUSY;
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csio_wr_reg32(hw, addr & ~0x3fU, EDC_BIST_CMD_ADDR + idx);
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csio_wr_reg32(hw, 64, EDC_BIST_CMD_LEN + idx);
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csio_wr_reg32(hw, 0xc, EDC_BIST_DATA_PATTERN + idx);
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csio_wr_reg32(hw, BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST,
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EDC_BIST_CMD + idx);
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i = csio_hw_wait_op_done_val(hw, EDC_BIST_CMD + idx, START_BIST,
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0, 10, 1, NULL);
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if (i)
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return i;
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#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx)
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for (i = 15; i >= 0; i--)
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*data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i)));
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if (ecc)
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*ecc = csio_rd_reg64(hw, EDC_DATA(16));
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#undef EDC_DATA
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return 0;
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}
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/*
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* csio_t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
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* @hw: the csio_hw
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* @win: PCI-E memory Window to use
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* @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_MC0 (or MEM_MC) or MEM_MC1
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* @addr: address within indicated memory type
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* @len: amount of memory to transfer
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* @buf: host memory buffer
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* @dir: direction of transfer 1 => read, 0 => write
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*
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* Reads/writes an [almost] arbitrary memory region in the firmware: the
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* firmware memory address, length and host buffer must be aligned on
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* 32-bit boudaries. The memory is transferred as a raw byte sequence
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* from/to the firmware's memory. If this memory contains data
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* structures which contain multi-byte integers, it's the callers
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* responsibility to perform appropriate byte order conversions.
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*/
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static int
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csio_t4_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
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u32 len, uint32_t *buf, int dir)
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{
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u32 pos, start, offset, memoffset, bar0;
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u32 edc_size, mc_size, mem_reg, mem_aperture, mem_base;
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/*
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* Argument sanity checks ...
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*/
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if ((addr & 0x3) || (len & 0x3))
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return -EINVAL;
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/* Offset into the region of memory which is being accessed
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* MEM_EDC0 = 0
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* MEM_EDC1 = 1
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* MEM_MC = 2 -- T4
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*/
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edc_size = EDRAM_SIZE_GET(csio_rd_reg32(hw, MA_EDRAM0_BAR));
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if (mtype != MEM_MC1)
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memoffset = (mtype * (edc_size * 1024 * 1024));
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else {
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mc_size = EXT_MEM_SIZE_GET(csio_rd_reg32(hw,
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MA_EXT_MEMORY_BAR));
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memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
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}
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/* Determine the PCIE_MEM_ACCESS_OFFSET */
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addr = addr + memoffset;
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/*
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* Each PCI-E Memory Window is programmed with a window size -- or
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* "aperture" -- which controls the granularity of its mapping onto
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* adapter memory. We need to grab that aperture in order to know
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* how to use the specified window. The window is also programmed
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* with the base address of the Memory Window in BAR0's address
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|
* space. For T4 this is an absolute PCI-E Bus Address. For T5
|
||
|
|
* the address is relative to BAR0.
|
||
|
|
*/
|
||
|
|
mem_reg = csio_rd_reg32(hw,
|
||
|
|
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
|
||
|
|
mem_aperture = 1 << (WINDOW(mem_reg) + 10);
|
||
|
|
mem_base = GET_PCIEOFST(mem_reg) << 10;
|
||
|
|
|
||
|
|
bar0 = csio_t4_read_pcie_cfg4(hw, PCI_BASE_ADDRESS_0);
|
||
|
|
bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
|
||
|
|
mem_base -= bar0;
|
||
|
|
|
||
|
|
start = addr & ~(mem_aperture-1);
|
||
|
|
offset = addr - start;
|
||
|
|
|
||
|
|
csio_dbg(hw, "csio_t4_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n",
|
||
|
|
mem_reg, mem_aperture);
|
||
|
|
csio_dbg(hw, "csio_t4_memory_rw: mem_base: 0x%x, mem_offset: 0x%x\n",
|
||
|
|
mem_base, memoffset);
|
||
|
|
csio_dbg(hw, "csio_t4_memory_rw: bar0: 0x%x, start:0x%x, offset:0x%x\n",
|
||
|
|
bar0, start, offset);
|
||
|
|
csio_dbg(hw, "csio_t4_memory_rw: mtype: %d, addr: 0x%x, len: %d\n",
|
||
|
|
mtype, addr, len);
|
||
|
|
|
||
|
|
for (pos = start; len > 0; pos += mem_aperture, offset = 0) {
|
||
|
|
/*
|
||
|
|
* Move PCI-E Memory Window to our current transfer
|
||
|
|
* position. Read it back to ensure that changes propagate
|
||
|
|
* before we attempt to use the new value.
|
||
|
|
*/
|
||
|
|
csio_wr_reg32(hw, pos,
|
||
|
|
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
|
||
|
|
csio_rd_reg32(hw,
|
||
|
|
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
|
||
|
|
|
||
|
|
while (offset < mem_aperture && len > 0) {
|
||
|
|
if (dir)
|
||
|
|
*buf++ = csio_rd_reg32(hw, mem_base + offset);
|
||
|
|
else
|
||
|
|
csio_wr_reg32(hw, *buf++, mem_base + offset);
|
||
|
|
|
||
|
|
offset += sizeof(__be32);
|
||
|
|
len -= sizeof(__be32);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* csio_t4_dfs_create_ext_mem - setup debugfs for MC to read the values
|
||
|
|
* @hw: the csio_hw
|
||
|
|
*
|
||
|
|
* This function creates files in the debugfs with external memory region MC.
|
||
|
|
*/
|
||
|
|
static void
|
||
|
|
csio_t4_dfs_create_ext_mem(struct csio_hw *hw)
|
||
|
|
{
|
||
|
|
u32 size;
|
||
|
|
int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE);
|
||
|
|
if (i & EXT_MEM_ENABLE) {
|
||
|
|
size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR);
|
||
|
|
csio_add_debugfs_mem(hw, "mc", MEM_MC,
|
||
|
|
EXT_MEM_SIZE_GET(size));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* T4 adapter specific function */
|
||
|
|
struct csio_hw_chip_ops t4_ops = {
|
||
|
|
.chip_set_mem_win = csio_t4_set_mem_win,
|
||
|
|
.chip_pcie_intr_handler = csio_t4_pcie_intr_handler,
|
||
|
|
.chip_flash_cfg_addr = csio_t4_flash_cfg_addr,
|
||
|
|
.chip_mc_read = csio_t4_mc_read,
|
||
|
|
.chip_edc_read = csio_t4_edc_read,
|
||
|
|
.chip_memory_rw = csio_t4_memory_rw,
|
||
|
|
.chip_dfs_create_ext_mem = csio_t4_dfs_create_ext_mem,
|
||
|
|
};
|