285 lines
9.8 KiB
C
285 lines
9.8 KiB
C
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/*
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* Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _DXE_H_
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#define _DXE_H_
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#include "wcn36xx.h"
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/*
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TX_LOW = DMA0
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TX_HIGH = DMA4
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RX_LOW = DMA1
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RX_HIGH = DMA3
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H2H_TEST_RX_TX = DMA2
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*/
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/* DXE registers */
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#define WCN36XX_DXE_MEM_REG 0x202000
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#define WCN36XX_DXE_CCU_INT 0xA0011
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#define WCN36XX_DXE_REG_CCU_INT_3660 0x200b10
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#define WCN36XX_DXE_REG_CCU_INT_3680 0x2050dc
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/* TODO This must calculated properly but not hardcoded */
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#define WCN36XX_DXE_CTRL_TX_L 0x328a44
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#define WCN36XX_DXE_CTRL_TX_H 0x32ce44
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#define WCN36XX_DXE_CTRL_RX_L 0x12ad2f
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#define WCN36XX_DXE_CTRL_RX_H 0x12d12f
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#define WCN36XX_DXE_CTRL_TX_H_BD 0x30ce45
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#define WCN36XX_DXE_CTRL_TX_H_SKB 0x32ce4d
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#define WCN36XX_DXE_CTRL_TX_L_BD 0x308a45
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#define WCN36XX_DXE_CTRL_TX_L_SKB 0x328a4d
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/* TODO This must calculated properly but not hardcoded */
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#define WCN36XX_DXE_WQ_TX_L 0x17
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#define WCN36XX_DXE_WQ_TX_H 0x17
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#define WCN36XX_DXE_WQ_RX_L 0xB
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#define WCN36XX_DXE_WQ_RX_H 0x4
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/* DXE descriptor control filed */
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#define WCN36XX_DXE_CTRL_VALID_MASK (0x00000001)
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/* TODO This must calculated properly but not hardcoded */
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/* DXE default control register values */
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#define WCN36XX_DXE_CH_DEFAULT_CTL_RX_L 0x847EAD2F
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#define WCN36XX_DXE_CH_DEFAULT_CTL_RX_H 0x84FED12F
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#define WCN36XX_DXE_CH_DEFAULT_CTL_TX_H 0x853ECF4D
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#define WCN36XX_DXE_CH_DEFAULT_CTL_TX_L 0x843e8b4d
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/* Common DXE registers */
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#define WCN36XX_DXE_MEM_CSR (WCN36XX_DXE_MEM_REG + 0x00)
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#define WCN36XX_DXE_REG_CSR_RESET (WCN36XX_DXE_MEM_REG + 0x00)
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#define WCN36XX_DXE_ENCH_ADDR (WCN36XX_DXE_MEM_REG + 0x04)
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#define WCN36XX_DXE_REG_CH_EN (WCN36XX_DXE_MEM_REG + 0x08)
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#define WCN36XX_DXE_REG_CH_DONE (WCN36XX_DXE_MEM_REG + 0x0C)
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#define WCN36XX_DXE_REG_CH_ERR (WCN36XX_DXE_MEM_REG + 0x10)
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#define WCN36XX_DXE_INT_MASK_REG (WCN36XX_DXE_MEM_REG + 0x18)
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#define WCN36XX_DXE_INT_SRC_RAW_REG (WCN36XX_DXE_MEM_REG + 0x20)
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/* #define WCN36XX_DXE_INT_CH6_MASK 0x00000040 */
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/* #define WCN36XX_DXE_INT_CH5_MASK 0x00000020 */
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#define WCN36XX_DXE_INT_CH4_MASK 0x00000010
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#define WCN36XX_DXE_INT_CH3_MASK 0x00000008
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/* #define WCN36XX_DXE_INT_CH2_MASK 0x00000004 */
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#define WCN36XX_DXE_INT_CH1_MASK 0x00000002
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#define WCN36XX_DXE_INT_CH0_MASK 0x00000001
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#define WCN36XX_DXE_0_INT_CLR (WCN36XX_DXE_MEM_REG + 0x30)
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#define WCN36XX_DXE_0_INT_ED_CLR (WCN36XX_DXE_MEM_REG + 0x34)
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#define WCN36XX_DXE_0_INT_DONE_CLR (WCN36XX_DXE_MEM_REG + 0x38)
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#define WCN36XX_DXE_0_INT_ERR_CLR (WCN36XX_DXE_MEM_REG + 0x3C)
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#define WCN36XX_DXE_0_CH0_STATUS (WCN36XX_DXE_MEM_REG + 0x404)
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#define WCN36XX_DXE_0_CH1_STATUS (WCN36XX_DXE_MEM_REG + 0x444)
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#define WCN36XX_DXE_0_CH2_STATUS (WCN36XX_DXE_MEM_REG + 0x484)
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#define WCN36XX_DXE_0_CH3_STATUS (WCN36XX_DXE_MEM_REG + 0x4C4)
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#define WCN36XX_DXE_0_CH4_STATUS (WCN36XX_DXE_MEM_REG + 0x504)
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#define WCN36XX_DXE_REG_RESET 0x5c89
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/* Temporary BMU Workqueue 4 */
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#define WCN36XX_DXE_BMU_WQ_RX_LOW 0xB
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#define WCN36XX_DXE_BMU_WQ_RX_HIGH 0x4
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/* DMA channel offset */
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#define WCN36XX_DXE_TX_LOW_OFFSET 0x400
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#define WCN36XX_DXE_TX_HIGH_OFFSET 0x500
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#define WCN36XX_DXE_RX_LOW_OFFSET 0x440
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#define WCN36XX_DXE_RX_HIGH_OFFSET 0x4C0
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/* Address of the next DXE descriptor */
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#define WCN36XX_DXE_CH_NEXT_DESC_ADDR 0x001C
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#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_TX_LOW_OFFSET + \
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WCN36XX_DXE_CH_NEXT_DESC_ADDR)
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#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_TX_HIGH_OFFSET + \
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WCN36XX_DXE_CH_NEXT_DESC_ADDR)
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#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_RX_LOW_OFFSET + \
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WCN36XX_DXE_CH_NEXT_DESC_ADDR)
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#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_RX_HIGH_OFFSET + \
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WCN36XX_DXE_CH_NEXT_DESC_ADDR)
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/* DXE Descriptor source address */
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#define WCN36XX_DXE_CH_SRC_ADDR 0x000C
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#define WCN36XX_DXE_CH_SRC_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_RX_LOW_OFFSET + \
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WCN36XX_DXE_CH_SRC_ADDR)
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#define WCN36XX_DXE_CH_SRC_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_RX_HIGH_OFFSET + \
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WCN36XX_DXE_CH_SRC_ADDR)
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/* DXE Descriptor address destination address */
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#define WCN36XX_DXE_CH_DEST_ADDR 0x0014
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#define WCN36XX_DXE_CH_DEST_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_TX_LOW_OFFSET + \
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WCN36XX_DXE_CH_DEST_ADDR)
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#define WCN36XX_DXE_CH_DEST_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_TX_HIGH_OFFSET + \
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WCN36XX_DXE_CH_DEST_ADDR)
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#define WCN36XX_DXE_CH_DEST_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_RX_LOW_OFFSET + \
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WCN36XX_DXE_CH_DEST_ADDR)
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#define WCN36XX_DXE_CH_DEST_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_RX_HIGH_OFFSET + \
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WCN36XX_DXE_CH_DEST_ADDR)
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/* Interrupt status */
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#define WCN36XX_DXE_CH_STATUS_REG_ADDR 0x0004
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#define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_TX_LOW_OFFSET + \
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WCN36XX_DXE_CH_STATUS_REG_ADDR)
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#define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_TX_HIGH_OFFSET + \
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WCN36XX_DXE_CH_STATUS_REG_ADDR)
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#define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_RX_LOW_OFFSET + \
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WCN36XX_DXE_CH_STATUS_REG_ADDR)
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#define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_RX_HIGH_OFFSET + \
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WCN36XX_DXE_CH_STATUS_REG_ADDR)
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/* DXE default control register */
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#define WCN36XX_DXE_REG_CTL_RX_L (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_RX_LOW_OFFSET)
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#define WCN36XX_DXE_REG_CTL_RX_H (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_RX_HIGH_OFFSET)
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#define WCN36XX_DXE_REG_CTL_TX_H (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_TX_HIGH_OFFSET)
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#define WCN36XX_DXE_REG_CTL_TX_L (WCN36XX_DXE_MEM_REG + \
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WCN36XX_DXE_TX_LOW_OFFSET)
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#define WCN36XX_SMSM_WLAN_TX_ENABLE 0x00000400
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#define WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY 0x00000200
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/* Interrupt control channel mask */
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#define WCN36XX_INT_MASK_CHAN_TX_L 0x00000001
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#define WCN36XX_INT_MASK_CHAN_RX_L 0x00000002
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#define WCN36XX_INT_MASK_CHAN_RX_H 0x00000008
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#define WCN36XX_INT_MASK_CHAN_TX_H 0x00000010
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#define WCN36XX_BD_CHUNK_SIZE 128
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#define WCN36XX_PKT_SIZE 0xF20
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enum wcn36xx_dxe_ch_type {
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WCN36XX_DXE_CH_TX_L,
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WCN36XX_DXE_CH_TX_H,
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WCN36XX_DXE_CH_RX_L,
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WCN36XX_DXE_CH_RX_H
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};
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/* amount of descriptors per channel */
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enum wcn36xx_dxe_ch_desc_num {
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WCN36XX_DXE_CH_DESC_NUMB_TX_L = 128,
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WCN36XX_DXE_CH_DESC_NUMB_TX_H = 10,
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WCN36XX_DXE_CH_DESC_NUMB_RX_L = 512,
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WCN36XX_DXE_CH_DESC_NUMB_RX_H = 40
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};
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/**
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* struct wcn36xx_dxe_desc - describes descriptor of one DXE buffer
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*
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* @ctrl: is a union that consists of following bits:
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* union {
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* u32 valid :1; //0 = DMA stop, 1 = DMA continue with this
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* //descriptor
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* u32 transfer_type :2; //0 = Host to Host space
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* u32 eop :1; //End of Packet
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* u32 bd_handling :1; //if transferType = Host to BMU, then 0
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* // means first 128 bytes contain BD, and 1
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* // means create new empty BD
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* u32 siq :1; // SIQ
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* u32 diq :1; // DIQ
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* u32 pdu_rel :1; //0 = don't release BD and PDUs when done,
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* // 1 = release them
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* u32 bthld_sel :4; //BMU Threshold Select
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* u32 prio :3; //Specifies the priority level to use for
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* // the transfer
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* u32 stop_channel :1; //1 = DMA stops processing further, channel
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* //requires re-enabling after this
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* u32 intr :1; //Interrupt on Descriptor Done
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* u32 rsvd :1; //reserved
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* u32 size :14;//14 bits used - ignored for BMU transfers,
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* //only used for host to host transfers?
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* } ctrl;
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*/
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struct wcn36xx_dxe_desc {
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u32 ctrl;
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u32 fr_len;
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u32 src_addr_l;
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u32 dst_addr_l;
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u32 phy_next_l;
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u32 src_addr_h;
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u32 dst_addr_h;
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u32 phy_next_h;
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} __packed;
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/* DXE Control block */
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struct wcn36xx_dxe_ctl {
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struct wcn36xx_dxe_ctl *next;
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struct wcn36xx_dxe_desc *desc;
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unsigned int desc_phy_addr;
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int ctl_blk_order;
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struct sk_buff *skb;
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spinlock_t skb_lock;
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void *bd_cpu_addr;
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dma_addr_t bd_phy_addr;
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};
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struct wcn36xx_dxe_ch {
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enum wcn36xx_dxe_ch_type ch_type;
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void *cpu_addr;
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dma_addr_t dma_addr;
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enum wcn36xx_dxe_ch_desc_num desc_num;
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/* DXE control block ring */
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struct wcn36xx_dxe_ctl *head_blk_ctl;
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struct wcn36xx_dxe_ctl *tail_blk_ctl;
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/* DXE channel specific configs */
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u32 dxe_wq;
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u32 ctrl_bd;
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u32 ctrl_skb;
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u32 reg_ctrl;
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u32 def_ctrl;
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};
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/* Memory Pool for BD headers */
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struct wcn36xx_dxe_mem_pool {
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int chunk_size;
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void *virt_addr;
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dma_addr_t phy_addr;
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};
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struct wcn36xx_vif;
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int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn);
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void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn);
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void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn);
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int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn);
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void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn);
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int wcn36xx_dxe_init(struct wcn36xx *wcn);
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void wcn36xx_dxe_deinit(struct wcn36xx *wcn);
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int wcn36xx_dxe_init_channels(struct wcn36xx *wcn);
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int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
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struct wcn36xx_vif *vif_priv,
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struct sk_buff *skb,
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bool is_low);
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void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status);
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void *wcn36xx_dxe_get_next_bd(struct wcn36xx *wcn, bool is_low);
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#endif /* _DXE_H_ */
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