2024-09-09 08:52:07 +00:00
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/****************************************************************************
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2024-09-09 08:57:42 +00:00
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* Driver for Solarflare network controllers and boards
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2024-09-09 08:52:07 +00:00
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* Copyright 2005-2006 Fen Systems Ltd.
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2024-09-09 08:57:42 +00:00
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* Copyright 2006-2013 Solarflare Communications Inc.
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2024-09-09 08:52:07 +00:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#ifndef EFX_NIC_H
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#define EFX_NIC_H
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2024-09-09 08:57:42 +00:00
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#include <linux/net_tstamp.h>
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2024-09-09 08:52:07 +00:00
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#include <linux/i2c-algo-bit.h>
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#include "net_driver.h"
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#include "efx.h"
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#include "mcdi.h"
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enum {
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EFX_REV_FALCON_A0 = 0,
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EFX_REV_FALCON_A1 = 1,
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EFX_REV_FALCON_B0 = 2,
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EFX_REV_SIENA_A0 = 3,
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2024-09-09 08:57:42 +00:00
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EFX_REV_HUNT_A0 = 4,
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2024-09-09 08:52:07 +00:00
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};
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static inline int efx_nic_rev(struct efx_nic *efx)
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{
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return efx->type->revision;
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}
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2024-09-09 08:57:42 +00:00
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u32 efx_farch_fpga_ver(struct efx_nic *efx);
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2024-09-09 08:52:07 +00:00
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/* NIC has two interlinked PCI functions for the same port. */
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static inline bool efx_nic_is_dual_func(struct efx_nic *efx)
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{
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return efx_nic_rev(efx) < EFX_REV_FALCON_B0;
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}
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2024-09-09 08:57:42 +00:00
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/* Read the current event from the event queue */
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static inline efx_qword_t *efx_event(struct efx_channel *channel,
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unsigned int index)
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{
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return ((efx_qword_t *) (channel->eventq.buf.addr)) +
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(index & channel->eventq_mask);
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}
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/* See if an event is present
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*
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* We check both the high and low dword of the event for all ones. We
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* wrote all ones when we cleared the event, and no valid event can
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* have all ones in either its high or low dwords. This approach is
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* robust against reordering.
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*
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* Note that using a single 64-bit comparison is incorrect; even
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* though the CPU read will be atomic, the DMA write may not be.
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*/
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static inline int efx_event_present(efx_qword_t *event)
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{
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return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
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EFX_DWORD_IS_ALL_ONES(event->dword[1]));
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}
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/* Returns a pointer to the specified transmit descriptor in the TX
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* descriptor queue belonging to the specified channel.
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*/
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static inline efx_qword_t *
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efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
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{
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return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
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}
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/* Get partner of a TX queue, seen as part of the same net core queue */
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static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue)
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{
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if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
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return tx_queue - EFX_TXQ_TYPE_OFFLOAD;
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else
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return tx_queue + EFX_TXQ_TYPE_OFFLOAD;
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}
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/* Report whether this TX queue would be empty for the given write_count.
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* May return false negative.
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*/
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static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue,
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unsigned int write_count)
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{
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unsigned int empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
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if (empty_read_count == 0)
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return false;
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return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
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}
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/* Decide whether we can use TX PIO, ie. write packet data directly into
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* a buffer on the device. This can reduce latency at the expense of
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* throughput, so we only do this if both hardware and software TX rings
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* are empty. This also ensures that only one packet at a time can be
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* using the PIO buffer.
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*/
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static inline bool efx_nic_may_tx_pio(struct efx_tx_queue *tx_queue)
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{
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struct efx_tx_queue *partner = efx_tx_queue_partner(tx_queue);
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return tx_queue->piobuf &&
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__efx_nic_tx_is_empty(tx_queue, tx_queue->insert_count) &&
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__efx_nic_tx_is_empty(partner, partner->insert_count);
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}
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/* Decide whether to push a TX descriptor to the NIC vs merely writing
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* the doorbell. This can reduce latency when we are adding a single
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* descriptor to an empty queue, but is otherwise pointless. Further,
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* Falcon and Siena have hardware bugs (SF bug 33851) that may be
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* triggered if we don't check this.
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* We use the write_count used for the last doorbell push, to get the
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* NIC's view of the tx queue.
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*/
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static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
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unsigned int write_count)
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{
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bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count);
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tx_queue->empty_read_count = 0;
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return was_empty && tx_queue->write_count - write_count == 1;
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}
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/* Returns a pointer to the specified descriptor in the RX descriptor queue */
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static inline efx_qword_t *
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efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
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{
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return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
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}
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2024-09-09 08:52:07 +00:00
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enum {
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PHY_TYPE_NONE = 0,
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PHY_TYPE_TXC43128 = 1,
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PHY_TYPE_88E1111 = 2,
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PHY_TYPE_SFX7101 = 3,
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PHY_TYPE_QT2022C2 = 4,
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PHY_TYPE_PM8358 = 6,
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PHY_TYPE_SFT9001A = 8,
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PHY_TYPE_QT2025C = 9,
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PHY_TYPE_SFT9001B = 10,
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};
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#define FALCON_XMAC_LOOPBACKS \
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((1 << LOOPBACK_XGMII) | \
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(1 << LOOPBACK_XGXS) | \
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(1 << LOOPBACK_XAUI))
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/* Alignment of PCIe DMA boundaries (4KB) */
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#define EFX_PAGE_SIZE 4096
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/* Size and alignment of buffer table entries (same) */
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#define EFX_BUF_SIZE EFX_PAGE_SIZE
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2024-09-09 08:57:42 +00:00
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/* NIC-generic software stats */
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enum {
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GENERIC_STAT_rx_noskb_drops,
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GENERIC_STAT_rx_nodesc_trunc,
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GENERIC_STAT_COUNT
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};
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2024-09-09 08:52:07 +00:00
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/**
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* struct falcon_board_type - board operations and type information
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* @id: Board type id, as found in NVRAM
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* @init: Allocate resources and initialise peripheral hardware
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* @init_phy: Do board-specific PHY initialisation
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* @fini: Shut down hardware and free resources
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* @set_id_led: Set state of identifying LED or revert to automatic function
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* @monitor: Board-specific health check function
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*/
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struct falcon_board_type {
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u8 id;
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int (*init) (struct efx_nic *nic);
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void (*init_phy) (struct efx_nic *efx);
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void (*fini) (struct efx_nic *nic);
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void (*set_id_led) (struct efx_nic *efx, enum efx_led_mode mode);
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int (*monitor) (struct efx_nic *nic);
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};
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/**
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* struct falcon_board - board information
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* @type: Type of board
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* @major: Major rev. ('A', 'B' ...)
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* @minor: Minor rev. (0, 1, ...)
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* @i2c_adap: I2C adapter for on-board peripherals
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* @i2c_data: Data for bit-banging algorithm
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* @hwmon_client: I2C client for hardware monitor
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* @ioexp_client: I2C client for power/port control
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*/
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struct falcon_board {
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const struct falcon_board_type *type;
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int major;
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int minor;
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struct i2c_adapter i2c_adap;
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struct i2c_algo_bit_data i2c_data;
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struct i2c_client *hwmon_client, *ioexp_client;
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};
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2024-09-09 08:57:42 +00:00
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/**
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* struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device
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* @device_id: Controller's id for the device
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* @size: Size (in bytes)
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* @addr_len: Number of address bytes in read/write commands
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* @munge_address: Flag whether addresses should be munged.
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* Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
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* use bit 3 of the command byte as address bit A8, rather
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* than having a two-byte address. If this flag is set, then
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* commands should be munged in this way.
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* @erase_command: Erase command (or 0 if sector erase not needed).
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* @erase_size: Erase sector size (in bytes)
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* Erase commands affect sectors with this size and alignment.
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* This must be a power of two.
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* @block_size: Write block size (in bytes).
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* Write commands are limited to blocks with this size and alignment.
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*/
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struct falcon_spi_device {
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int device_id;
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unsigned int size;
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unsigned int addr_len;
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unsigned int munge_address:1;
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u8 erase_command;
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unsigned int erase_size;
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unsigned int block_size;
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};
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static inline bool falcon_spi_present(const struct falcon_spi_device *spi)
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{
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return spi->size != 0;
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}
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enum {
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FALCON_STAT_tx_bytes = GENERIC_STAT_COUNT,
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FALCON_STAT_tx_packets,
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FALCON_STAT_tx_pause,
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FALCON_STAT_tx_control,
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FALCON_STAT_tx_unicast,
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FALCON_STAT_tx_multicast,
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FALCON_STAT_tx_broadcast,
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FALCON_STAT_tx_lt64,
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FALCON_STAT_tx_64,
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FALCON_STAT_tx_65_to_127,
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FALCON_STAT_tx_128_to_255,
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FALCON_STAT_tx_256_to_511,
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FALCON_STAT_tx_512_to_1023,
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FALCON_STAT_tx_1024_to_15xx,
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FALCON_STAT_tx_15xx_to_jumbo,
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FALCON_STAT_tx_gtjumbo,
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FALCON_STAT_tx_non_tcpudp,
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FALCON_STAT_tx_mac_src_error,
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FALCON_STAT_tx_ip_src_error,
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FALCON_STAT_rx_bytes,
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FALCON_STAT_rx_good_bytes,
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FALCON_STAT_rx_bad_bytes,
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FALCON_STAT_rx_packets,
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FALCON_STAT_rx_good,
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FALCON_STAT_rx_bad,
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FALCON_STAT_rx_pause,
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FALCON_STAT_rx_control,
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FALCON_STAT_rx_unicast,
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FALCON_STAT_rx_multicast,
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FALCON_STAT_rx_broadcast,
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FALCON_STAT_rx_lt64,
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FALCON_STAT_rx_64,
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FALCON_STAT_rx_65_to_127,
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FALCON_STAT_rx_128_to_255,
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FALCON_STAT_rx_256_to_511,
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FALCON_STAT_rx_512_to_1023,
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FALCON_STAT_rx_1024_to_15xx,
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FALCON_STAT_rx_15xx_to_jumbo,
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FALCON_STAT_rx_gtjumbo,
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FALCON_STAT_rx_bad_lt64,
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FALCON_STAT_rx_bad_gtjumbo,
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FALCON_STAT_rx_overflow,
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FALCON_STAT_rx_symbol_error,
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FALCON_STAT_rx_align_error,
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FALCON_STAT_rx_length_error,
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FALCON_STAT_rx_internal_error,
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FALCON_STAT_rx_nodesc_drop_cnt,
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FALCON_STAT_COUNT
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};
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2024-09-09 08:52:07 +00:00
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/**
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* struct falcon_nic_data - Falcon NIC state
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* @pci_dev2: Secondary function of Falcon A
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* @board: Board state and functions
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2024-09-09 08:57:42 +00:00
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* @stats: Hardware statistics
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2024-09-09 08:52:07 +00:00
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* @stats_disable_count: Nest count for disabling statistics fetches
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* @stats_pending: Is there a pending DMA of MAC statistics.
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* @stats_timer: A timer for regularly fetching MAC statistics.
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* @spi_flash: SPI flash device
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* @spi_eeprom: SPI EEPROM device
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* @spi_lock: SPI bus lock
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* @mdio_lock: MDIO bus lock
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|
|
|
|
* @xmac_poll_required: XMAC link state needs polling
|
|
|
|
|
*/
|
|
|
|
|
struct falcon_nic_data {
|
|
|
|
|
struct pci_dev *pci_dev2;
|
|
|
|
|
struct falcon_board board;
|
2024-09-09 08:57:42 +00:00
|
|
|
u64 stats[FALCON_STAT_COUNT];
|
2024-09-09 08:52:07 +00:00
|
|
|
unsigned int stats_disable_count;
|
|
|
|
|
bool stats_pending;
|
|
|
|
|
struct timer_list stats_timer;
|
2024-09-09 08:57:42 +00:00
|
|
|
struct falcon_spi_device spi_flash;
|
|
|
|
|
struct falcon_spi_device spi_eeprom;
|
2024-09-09 08:52:07 +00:00
|
|
|
struct mutex spi_lock;
|
|
|
|
|
struct mutex mdio_lock;
|
|
|
|
|
bool xmac_poll_required;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static inline struct falcon_board *falcon_board(struct efx_nic *efx)
|
|
|
|
|
{
|
|
|
|
|
struct falcon_nic_data *data = efx->nic_data;
|
|
|
|
|
return &data->board;
|
|
|
|
|
}
|
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
enum {
|
|
|
|
|
SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT,
|
|
|
|
|
SIENA_STAT_tx_good_bytes,
|
|
|
|
|
SIENA_STAT_tx_bad_bytes,
|
|
|
|
|
SIENA_STAT_tx_packets,
|
|
|
|
|
SIENA_STAT_tx_bad,
|
|
|
|
|
SIENA_STAT_tx_pause,
|
|
|
|
|
SIENA_STAT_tx_control,
|
|
|
|
|
SIENA_STAT_tx_unicast,
|
|
|
|
|
SIENA_STAT_tx_multicast,
|
|
|
|
|
SIENA_STAT_tx_broadcast,
|
|
|
|
|
SIENA_STAT_tx_lt64,
|
|
|
|
|
SIENA_STAT_tx_64,
|
|
|
|
|
SIENA_STAT_tx_65_to_127,
|
|
|
|
|
SIENA_STAT_tx_128_to_255,
|
|
|
|
|
SIENA_STAT_tx_256_to_511,
|
|
|
|
|
SIENA_STAT_tx_512_to_1023,
|
|
|
|
|
SIENA_STAT_tx_1024_to_15xx,
|
|
|
|
|
SIENA_STAT_tx_15xx_to_jumbo,
|
|
|
|
|
SIENA_STAT_tx_gtjumbo,
|
|
|
|
|
SIENA_STAT_tx_collision,
|
|
|
|
|
SIENA_STAT_tx_single_collision,
|
|
|
|
|
SIENA_STAT_tx_multiple_collision,
|
|
|
|
|
SIENA_STAT_tx_excessive_collision,
|
|
|
|
|
SIENA_STAT_tx_deferred,
|
|
|
|
|
SIENA_STAT_tx_late_collision,
|
|
|
|
|
SIENA_STAT_tx_excessive_deferred,
|
|
|
|
|
SIENA_STAT_tx_non_tcpudp,
|
|
|
|
|
SIENA_STAT_tx_mac_src_error,
|
|
|
|
|
SIENA_STAT_tx_ip_src_error,
|
|
|
|
|
SIENA_STAT_rx_bytes,
|
|
|
|
|
SIENA_STAT_rx_good_bytes,
|
|
|
|
|
SIENA_STAT_rx_bad_bytes,
|
|
|
|
|
SIENA_STAT_rx_packets,
|
|
|
|
|
SIENA_STAT_rx_good,
|
|
|
|
|
SIENA_STAT_rx_bad,
|
|
|
|
|
SIENA_STAT_rx_pause,
|
|
|
|
|
SIENA_STAT_rx_control,
|
|
|
|
|
SIENA_STAT_rx_unicast,
|
|
|
|
|
SIENA_STAT_rx_multicast,
|
|
|
|
|
SIENA_STAT_rx_broadcast,
|
|
|
|
|
SIENA_STAT_rx_lt64,
|
|
|
|
|
SIENA_STAT_rx_64,
|
|
|
|
|
SIENA_STAT_rx_65_to_127,
|
|
|
|
|
SIENA_STAT_rx_128_to_255,
|
|
|
|
|
SIENA_STAT_rx_256_to_511,
|
|
|
|
|
SIENA_STAT_rx_512_to_1023,
|
|
|
|
|
SIENA_STAT_rx_1024_to_15xx,
|
|
|
|
|
SIENA_STAT_rx_15xx_to_jumbo,
|
|
|
|
|
SIENA_STAT_rx_gtjumbo,
|
|
|
|
|
SIENA_STAT_rx_bad_gtjumbo,
|
|
|
|
|
SIENA_STAT_rx_overflow,
|
|
|
|
|
SIENA_STAT_rx_false_carrier,
|
|
|
|
|
SIENA_STAT_rx_symbol_error,
|
|
|
|
|
SIENA_STAT_rx_align_error,
|
|
|
|
|
SIENA_STAT_rx_length_error,
|
|
|
|
|
SIENA_STAT_rx_internal_error,
|
|
|
|
|
SIENA_STAT_rx_nodesc_drop_cnt,
|
|
|
|
|
SIENA_STAT_COUNT
|
|
|
|
|
};
|
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
/**
|
|
|
|
|
* struct siena_nic_data - Siena NIC state
|
|
|
|
|
* @wol_filter_id: Wake-on-LAN packet filter id
|
2024-09-09 08:57:42 +00:00
|
|
|
* @stats: Hardware statistics
|
2024-09-09 08:52:07 +00:00
|
|
|
*/
|
|
|
|
|
struct siena_nic_data {
|
|
|
|
|
int wol_filter_id;
|
2024-09-09 08:57:42 +00:00
|
|
|
u64 stats[SIENA_STAT_COUNT];
|
2024-09-09 08:52:07 +00:00
|
|
|
};
|
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
enum {
|
|
|
|
|
EF10_STAT_tx_bytes = GENERIC_STAT_COUNT,
|
|
|
|
|
EF10_STAT_tx_packets,
|
|
|
|
|
EF10_STAT_tx_pause,
|
|
|
|
|
EF10_STAT_tx_control,
|
|
|
|
|
EF10_STAT_tx_unicast,
|
|
|
|
|
EF10_STAT_tx_multicast,
|
|
|
|
|
EF10_STAT_tx_broadcast,
|
|
|
|
|
EF10_STAT_tx_lt64,
|
|
|
|
|
EF10_STAT_tx_64,
|
|
|
|
|
EF10_STAT_tx_65_to_127,
|
|
|
|
|
EF10_STAT_tx_128_to_255,
|
|
|
|
|
EF10_STAT_tx_256_to_511,
|
|
|
|
|
EF10_STAT_tx_512_to_1023,
|
|
|
|
|
EF10_STAT_tx_1024_to_15xx,
|
|
|
|
|
EF10_STAT_tx_15xx_to_jumbo,
|
|
|
|
|
EF10_STAT_rx_bytes,
|
|
|
|
|
EF10_STAT_rx_bytes_minus_good_bytes,
|
|
|
|
|
EF10_STAT_rx_good_bytes,
|
|
|
|
|
EF10_STAT_rx_bad_bytes,
|
|
|
|
|
EF10_STAT_rx_packets,
|
|
|
|
|
EF10_STAT_rx_good,
|
|
|
|
|
EF10_STAT_rx_bad,
|
|
|
|
|
EF10_STAT_rx_pause,
|
|
|
|
|
EF10_STAT_rx_control,
|
|
|
|
|
EF10_STAT_rx_unicast,
|
|
|
|
|
EF10_STAT_rx_multicast,
|
|
|
|
|
EF10_STAT_rx_broadcast,
|
|
|
|
|
EF10_STAT_rx_lt64,
|
|
|
|
|
EF10_STAT_rx_64,
|
|
|
|
|
EF10_STAT_rx_65_to_127,
|
|
|
|
|
EF10_STAT_rx_128_to_255,
|
|
|
|
|
EF10_STAT_rx_256_to_511,
|
|
|
|
|
EF10_STAT_rx_512_to_1023,
|
|
|
|
|
EF10_STAT_rx_1024_to_15xx,
|
|
|
|
|
EF10_STAT_rx_15xx_to_jumbo,
|
|
|
|
|
EF10_STAT_rx_gtjumbo,
|
|
|
|
|
EF10_STAT_rx_bad_gtjumbo,
|
|
|
|
|
EF10_STAT_rx_overflow,
|
|
|
|
|
EF10_STAT_rx_align_error,
|
|
|
|
|
EF10_STAT_rx_length_error,
|
|
|
|
|
EF10_STAT_rx_nodesc_drops,
|
|
|
|
|
EF10_STAT_rx_pm_trunc_bb_overflow,
|
|
|
|
|
EF10_STAT_rx_pm_discard_bb_overflow,
|
|
|
|
|
EF10_STAT_rx_pm_trunc_vfifo_full,
|
|
|
|
|
EF10_STAT_rx_pm_discard_vfifo_full,
|
|
|
|
|
EF10_STAT_rx_pm_trunc_qbb,
|
|
|
|
|
EF10_STAT_rx_pm_discard_qbb,
|
|
|
|
|
EF10_STAT_rx_pm_discard_mapping,
|
|
|
|
|
EF10_STAT_rx_dp_q_disabled_packets,
|
|
|
|
|
EF10_STAT_rx_dp_di_dropped_packets,
|
|
|
|
|
EF10_STAT_rx_dp_streaming_packets,
|
|
|
|
|
EF10_STAT_rx_dp_hlb_fetch,
|
|
|
|
|
EF10_STAT_rx_dp_hlb_wait,
|
|
|
|
|
EF10_STAT_COUNT
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Maximum number of TX PIO buffers we may allocate to a function.
|
|
|
|
|
* This matches the total number of buffers on each SFC9100-family
|
|
|
|
|
* controller.
|
|
|
|
|
*/
|
|
|
|
|
#define EF10_TX_PIOBUF_COUNT 16
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* struct efx_ef10_nic_data - EF10 architecture NIC state
|
|
|
|
|
* @mcdi_buf: DMA buffer for MCDI
|
|
|
|
|
* @warm_boot_count: Last seen MC warm boot count
|
|
|
|
|
* @vi_base: Absolute index of first VI in this function
|
|
|
|
|
* @n_allocated_vis: Number of VIs allocated to this function
|
|
|
|
|
* @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
|
|
|
|
|
* @must_restore_filters: Flag: filters have yet to be restored after MC reboot
|
|
|
|
|
* @n_piobufs: Number of PIO buffers allocated to this function
|
|
|
|
|
* @wc_membase: Base address of write-combining mapping of the memory BAR
|
|
|
|
|
* @pio_write_base: Base address for writing PIO buffers
|
|
|
|
|
* @pio_write_vi_base: Relative VI number for @pio_write_base
|
|
|
|
|
* @piobuf_handle: Handle of each PIO buffer allocated
|
|
|
|
|
* @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
|
|
|
|
|
* reboot
|
|
|
|
|
* @rx_rss_context: Firmware handle for our RSS context
|
|
|
|
|
* @stats: Hardware statistics
|
|
|
|
|
* @workaround_35388: Flag: firmware supports workaround for bug 35388
|
|
|
|
|
* @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
|
|
|
|
|
* after MC reboot
|
|
|
|
|
* @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
|
|
|
|
|
* %MC_CMD_GET_CAPABILITIES response)
|
|
|
|
|
*/
|
|
|
|
|
struct efx_ef10_nic_data {
|
|
|
|
|
struct efx_buffer mcdi_buf;
|
|
|
|
|
u16 warm_boot_count;
|
|
|
|
|
unsigned int vi_base;
|
|
|
|
|
unsigned int n_allocated_vis;
|
|
|
|
|
bool must_realloc_vis;
|
|
|
|
|
bool must_restore_filters;
|
|
|
|
|
unsigned int n_piobufs;
|
|
|
|
|
void __iomem *wc_membase, *pio_write_base;
|
|
|
|
|
unsigned int pio_write_vi_base;
|
|
|
|
|
unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
|
|
|
|
|
bool must_restore_piobufs;
|
|
|
|
|
u32 rx_rss_context;
|
|
|
|
|
u64 stats[EF10_STAT_COUNT];
|
|
|
|
|
bool workaround_35388;
|
|
|
|
|
bool must_check_datapath_caps;
|
|
|
|
|
u32 datapath_caps;
|
|
|
|
|
};
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* On the SFC9000 family each port is associated with 1 PCI physical
|
|
|
|
|
* function (PF) handled by sfc and a configurable number of virtual
|
|
|
|
|
* functions (VFs) that may be handled by some other driver, often in
|
|
|
|
|
* a VM guest. The queue pointer registers are mapped in both PF and
|
|
|
|
|
* VF BARs such that an 8K region provides access to a single RX, TX
|
|
|
|
|
* and event queue (collectively a Virtual Interface, VI or VNIC).
|
|
|
|
|
*
|
|
|
|
|
* The PF has access to all 1024 VIs while VFs are mapped to VIs
|
|
|
|
|
* according to VI_BASE and VI_SCALE: VF i has access to VIs numbered
|
|
|
|
|
* in range [VI_BASE + i << VI_SCALE, VI_BASE + i + 1 << VI_SCALE).
|
|
|
|
|
* The number of VIs and the VI_SCALE value are configurable but must
|
|
|
|
|
* be established at boot time by firmware.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* Maximum VI_SCALE parameter supported by Siena */
|
|
|
|
|
#define EFX_VI_SCALE_MAX 6
|
|
|
|
|
/* Base VI to use for SR-IOV. Must be aligned to (1 << EFX_VI_SCALE_MAX),
|
|
|
|
|
* so this is the smallest allowed value. */
|
|
|
|
|
#define EFX_VI_BASE 128U
|
|
|
|
|
/* Maximum number of VFs allowed */
|
|
|
|
|
#define EFX_VF_COUNT_MAX 127
|
|
|
|
|
/* Limit EVQs on VFs to be only 8k to reduce buffer table reservation */
|
|
|
|
|
#define EFX_MAX_VF_EVQ_SIZE 8192UL
|
|
|
|
|
/* The number of buffer table entries reserved for each VI on a VF */
|
|
|
|
|
#define EFX_VF_BUFTBL_PER_VI \
|
|
|
|
|
((EFX_MAX_VF_EVQ_SIZE + 2 * EFX_MAX_DMAQ_SIZE) * \
|
|
|
|
|
sizeof(efx_qword_t) / EFX_BUF_SIZE)
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SFC_SRIOV
|
|
|
|
|
|
|
|
|
|
static inline bool efx_sriov_wanted(struct efx_nic *efx)
|
|
|
|
|
{
|
|
|
|
|
return efx->vf_count != 0;
|
|
|
|
|
}
|
|
|
|
|
static inline bool efx_sriov_enabled(struct efx_nic *efx)
|
|
|
|
|
{
|
|
|
|
|
return efx->vf_init_count != 0;
|
|
|
|
|
}
|
|
|
|
|
static inline unsigned int efx_vf_size(struct efx_nic *efx)
|
|
|
|
|
{
|
|
|
|
|
return 1 << efx->vi_scale;
|
|
|
|
|
}
|
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
int efx_init_sriov(void);
|
|
|
|
|
void efx_sriov_probe(struct efx_nic *efx);
|
|
|
|
|
int efx_sriov_init(struct efx_nic *efx);
|
|
|
|
|
void efx_sriov_mac_address_changed(struct efx_nic *efx);
|
|
|
|
|
void efx_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event);
|
|
|
|
|
void efx_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event);
|
|
|
|
|
void efx_sriov_event(struct efx_channel *channel, efx_qword_t *event);
|
|
|
|
|
void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq);
|
|
|
|
|
void efx_sriov_flr(struct efx_nic *efx, unsigned flr);
|
|
|
|
|
void efx_sriov_reset(struct efx_nic *efx);
|
|
|
|
|
void efx_sriov_fini(struct efx_nic *efx);
|
|
|
|
|
void efx_fini_sriov(void);
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
|
|
static inline bool efx_sriov_wanted(struct efx_nic *efx) { return false; }
|
|
|
|
|
static inline bool efx_sriov_enabled(struct efx_nic *efx) { return false; }
|
|
|
|
|
static inline unsigned int efx_vf_size(struct efx_nic *efx) { return 0; }
|
|
|
|
|
|
|
|
|
|
static inline int efx_init_sriov(void) { return 0; }
|
|
|
|
|
static inline void efx_sriov_probe(struct efx_nic *efx) {}
|
|
|
|
|
static inline int efx_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; }
|
|
|
|
|
static inline void efx_sriov_mac_address_changed(struct efx_nic *efx) {}
|
|
|
|
|
static inline void efx_sriov_tx_flush_done(struct efx_nic *efx,
|
|
|
|
|
efx_qword_t *event) {}
|
|
|
|
|
static inline void efx_sriov_rx_flush_done(struct efx_nic *efx,
|
|
|
|
|
efx_qword_t *event) {}
|
|
|
|
|
static inline void efx_sriov_event(struct efx_channel *channel,
|
|
|
|
|
efx_qword_t *event) {}
|
|
|
|
|
static inline void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq) {}
|
|
|
|
|
static inline void efx_sriov_flr(struct efx_nic *efx, unsigned flr) {}
|
|
|
|
|
static inline void efx_sriov_reset(struct efx_nic *efx) {}
|
|
|
|
|
static inline void efx_sriov_fini(struct efx_nic *efx) {}
|
|
|
|
|
static inline void efx_fini_sriov(void) {}
|
|
|
|
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#endif
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|
2024-09-09 08:57:42 +00:00
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int efx_sriov_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
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int efx_sriov_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos);
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int efx_sriov_get_vf_config(struct net_device *dev, int vf,
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struct ifla_vf_info *ivf);
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int efx_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf,
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bool spoofchk);
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struct ethtool_ts_info;
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int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel);
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void efx_ptp_defer_probe_with_channel(struct efx_nic *efx);
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void efx_ptp_remove(struct efx_nic *efx);
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int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr);
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int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr);
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void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info);
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bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
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int efx_ptp_get_mode(struct efx_nic *efx);
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int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted,
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|
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unsigned int new_mode);
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int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
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void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev);
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size_t efx_ptp_describe_stats(struct efx_nic *efx, u8 *strings);
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size_t efx_ptp_update_stats(struct efx_nic *efx, u64 *stats);
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void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev);
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void __efx_rx_skb_attach_timestamp(struct efx_channel *channel,
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struct sk_buff *skb);
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static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel,
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struct sk_buff *skb)
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{
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if (channel->sync_events_state == SYNC_EVENTS_VALID)
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__efx_rx_skb_attach_timestamp(channel, skb);
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}
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void efx_ptp_start_datapath(struct efx_nic *efx);
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void efx_ptp_stop_datapath(struct efx_nic *efx);
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2024-09-09 08:52:07 +00:00
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extern const struct efx_nic_type falcon_a1_nic_type;
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extern const struct efx_nic_type falcon_b0_nic_type;
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extern const struct efx_nic_type siena_a0_nic_type;
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2024-09-09 08:57:42 +00:00
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extern const struct efx_nic_type efx_hunt_a0_nic_type;
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2024-09-09 08:52:07 +00:00
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/**************************************************************************
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*
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* Externs
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*
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**************************************************************************
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*/
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2024-09-09 08:57:42 +00:00
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int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
|
2024-09-09 08:52:07 +00:00
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/* TX data path */
|
2024-09-09 08:57:42 +00:00
|
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static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
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|
{
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|
return tx_queue->efx->type->tx_probe(tx_queue);
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}
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static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
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|
{
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|
tx_queue->efx->type->tx_init(tx_queue);
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}
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static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
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|
{
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|
tx_queue->efx->type->tx_remove(tx_queue);
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}
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static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
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|
|
{
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|
tx_queue->efx->type->tx_write(tx_queue);
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|
}
|
2024-09-09 08:52:07 +00:00
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|
/* RX data path */
|
2024-09-09 08:57:42 +00:00
|
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|
static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
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|
|
{
|
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|
|
return rx_queue->efx->type->rx_probe(rx_queue);
|
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|
}
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|
static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
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|
|
{
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|
|
rx_queue->efx->type->rx_init(rx_queue);
|
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|
|
}
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|
static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
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|
|
{
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|
|
|
rx_queue->efx->type->rx_remove(rx_queue);
|
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|
|
}
|
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|
static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
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|
|
|
{
|
|
|
|
|
rx_queue->efx->type->rx_write(rx_queue);
|
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|
|
}
|
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|
static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
|
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|
|
|
{
|
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|
|
rx_queue->efx->type->rx_defer_refill(rx_queue);
|
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|
|
|
}
|
2024-09-09 08:52:07 +00:00
|
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|
|
/* Event data path */
|
2024-09-09 08:57:42 +00:00
|
|
|
static inline int efx_nic_probe_eventq(struct efx_channel *channel)
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|
|
|
|
{
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|
|
|
|
return channel->efx->type->ev_probe(channel);
|
|
|
|
|
}
|
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|
|
static inline int efx_nic_init_eventq(struct efx_channel *channel)
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|
|
|
{
|
|
|
|
|
return channel->efx->type->ev_init(channel);
|
|
|
|
|
}
|
|
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|
|
static inline void efx_nic_fini_eventq(struct efx_channel *channel)
|
|
|
|
|
{
|
|
|
|
|
channel->efx->type->ev_fini(channel);
|
|
|
|
|
}
|
|
|
|
|
static inline void efx_nic_remove_eventq(struct efx_channel *channel)
|
|
|
|
|
{
|
|
|
|
|
channel->efx->type->ev_remove(channel);
|
|
|
|
|
}
|
|
|
|
|
static inline int
|
|
|
|
|
efx_nic_process_eventq(struct efx_channel *channel, int quota)
|
|
|
|
|
{
|
|
|
|
|
return channel->efx->type->ev_process(channel, quota);
|
|
|
|
|
}
|
|
|
|
|
static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
|
|
|
|
|
{
|
|
|
|
|
channel->efx->type->ev_read_ack(channel);
|
|
|
|
|
}
|
|
|
|
|
void efx_nic_event_test_start(struct efx_channel *channel);
|
|
|
|
|
|
|
|
|
|
/* Falcon/Siena queue operations */
|
|
|
|
|
int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
|
|
|
|
|
void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
|
|
|
|
|
void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
|
|
|
|
|
void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
|
|
|
|
|
void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
|
|
|
|
|
int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
|
|
|
|
|
void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
|
|
|
|
|
void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
|
|
|
|
|
void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
|
|
|
|
|
void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
|
|
|
|
|
void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
|
|
|
|
|
int efx_farch_ev_probe(struct efx_channel *channel);
|
|
|
|
|
int efx_farch_ev_init(struct efx_channel *channel);
|
|
|
|
|
void efx_farch_ev_fini(struct efx_channel *channel);
|
|
|
|
|
void efx_farch_ev_remove(struct efx_channel *channel);
|
|
|
|
|
int efx_farch_ev_process(struct efx_channel *channel, int quota);
|
|
|
|
|
void efx_farch_ev_read_ack(struct efx_channel *channel);
|
|
|
|
|
void efx_farch_ev_test_generate(struct efx_channel *channel);
|
|
|
|
|
|
|
|
|
|
/* Falcon/Siena filter operations */
|
|
|
|
|
int efx_farch_filter_table_probe(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_filter_table_restore(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_filter_table_remove(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
|
|
|
|
|
s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
|
|
|
|
|
bool replace);
|
|
|
|
|
int efx_farch_filter_remove_safe(struct efx_nic *efx,
|
|
|
|
|
enum efx_filter_priority priority,
|
|
|
|
|
u32 filter_id);
|
|
|
|
|
int efx_farch_filter_get_safe(struct efx_nic *efx,
|
|
|
|
|
enum efx_filter_priority priority, u32 filter_id,
|
|
|
|
|
struct efx_filter_spec *);
|
|
|
|
|
int efx_farch_filter_clear_rx(struct efx_nic *efx,
|
|
|
|
|
enum efx_filter_priority priority);
|
|
|
|
|
u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
|
|
|
|
|
enum efx_filter_priority priority);
|
|
|
|
|
u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
|
|
|
|
|
s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
|
|
|
|
|
enum efx_filter_priority priority, u32 *buf,
|
|
|
|
|
u32 size);
|
|
|
|
|
#ifdef CONFIG_RFS_ACCEL
|
|
|
|
|
s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
|
|
|
|
|
struct efx_filter_spec *spec);
|
|
|
|
|
bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
|
|
|
|
|
unsigned int index);
|
|
|
|
|
#endif
|
|
|
|
|
void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
|
|
|
|
|
|
|
|
|
|
bool efx_nic_event_present(struct efx_channel *channel);
|
|
|
|
|
|
|
|
|
|
/* Some statistics are computed as A - B where A and B each increase
|
|
|
|
|
* linearly with some hardware counter(s) and the counters are read
|
|
|
|
|
* asynchronously. If the counters contributing to B are always read
|
|
|
|
|
* after those contributing to A, the computed value may be lower than
|
|
|
|
|
* the true value by some variable amount, and may decrease between
|
|
|
|
|
* subsequent computations.
|
|
|
|
|
*
|
|
|
|
|
* We should never allow statistics to decrease or to exceed the true
|
|
|
|
|
* value. Since the computed value will never be greater than the
|
|
|
|
|
* true value, we can achieve this by only storing the computed value
|
|
|
|
|
* when it increases.
|
|
|
|
|
*/
|
|
|
|
|
static inline void efx_update_diff_stat(u64 *stat, u64 diff)
|
|
|
|
|
{
|
|
|
|
|
if ((s64)(diff - *stat) > 0)
|
|
|
|
|
*stat = diff;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Interrupts */
|
|
|
|
|
int efx_nic_init_interrupt(struct efx_nic *efx);
|
|
|
|
|
void efx_nic_irq_test_start(struct efx_nic *efx);
|
|
|
|
|
void efx_nic_fini_interrupt(struct efx_nic *efx);
|
|
|
|
|
|
|
|
|
|
/* Falcon/Siena interrupts */
|
|
|
|
|
void efx_farch_irq_enable_master(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_irq_test_generate(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_irq_disable_master(struct efx_nic *efx);
|
|
|
|
|
irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
|
|
|
|
|
irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
|
|
|
|
|
irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
|
static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
|
|
|
|
|
{
|
|
|
|
|
return ACCESS_ONCE(channel->event_test_cpu);
|
|
|
|
|
}
|
|
|
|
|
static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
|
|
|
|
|
{
|
|
|
|
|
return ACCESS_ONCE(efx->last_irq_cpu);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Global Resources */
|
2024-09-09 08:57:42 +00:00
|
|
|
int efx_nic_flush_queues(struct efx_nic *efx);
|
|
|
|
|
void siena_prepare_flush(struct efx_nic *efx);
|
|
|
|
|
int efx_farch_fini_dmaq(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_finish_flr(struct efx_nic *efx);
|
|
|
|
|
void siena_finish_flush(struct efx_nic *efx);
|
|
|
|
|
void falcon_start_nic_stats(struct efx_nic *efx);
|
|
|
|
|
void falcon_stop_nic_stats(struct efx_nic *efx);
|
|
|
|
|
int falcon_reset_xaui(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
|
|
|
|
|
void efx_farch_init_common(struct efx_nic *efx);
|
|
|
|
|
void efx_ef10_handle_drain_event(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_rx_push_indir_table(struct efx_nic *efx);
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
|
int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
|
2024-09-09 08:57:42 +00:00
|
|
|
unsigned int len, gfp_t gfp_flags);
|
2024-09-09 08:52:07 +00:00
|
|
|
void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
|
|
|
|
|
|
|
|
|
|
/* Tests */
|
2024-09-09 08:57:42 +00:00
|
|
|
struct efx_farch_register_test {
|
2024-09-09 08:52:07 +00:00
|
|
|
unsigned address;
|
|
|
|
|
efx_oword_t mask;
|
|
|
|
|
};
|
2024-09-09 08:57:42 +00:00
|
|
|
int efx_farch_test_registers(struct efx_nic *efx,
|
|
|
|
|
const struct efx_farch_register_test *regs,
|
|
|
|
|
size_t n_regs);
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
size_t efx_nic_get_regs_len(struct efx_nic *efx);
|
|
|
|
|
void efx_nic_get_regs(struct efx_nic *efx, void *buf);
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
|
|
|
|
|
const unsigned long *mask, u8 *names);
|
|
|
|
|
void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
|
|
|
|
|
const unsigned long *mask, u64 *stats,
|
|
|
|
|
const void *dma_buf, bool accumulate);
|
|
|
|
|
void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat);
|
|
|
|
|
|
|
|
|
|
#define EFX_MAX_FLUSH_TIME 5000
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
|
|
|
|
|
efx_qword_t *event);
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
|
#endif /* EFX_NIC_H */
|
