153 lines
6.2 KiB
C
153 lines
6.2 KiB
C
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/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _EMAC_SGMII_H_
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#define _EMAC_SGMII_H_
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#include "emac.h"
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/* EMAC_QSERDES register offsets */
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#define EMAC_QSERDES_COM_SYS_CLK_CTRL 0x000000
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#define EMAC_QSERDES_COM_PLL_VCOTAIL_EN 0x000004
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#define EMAC_QSERDES_COM_PLL_CNTRL 0x000014
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#define EMAC_QSERDES_COM_PLL_IP_SETI 0x000018
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#define EMAC_QSERDES_COM_PLL_CP_SETI 0x000024
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#define EMAC_QSERDES_COM_PLL_IP_SETP 0x000028
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#define EMAC_QSERDES_COM_PLL_CP_SETP 0x00002c
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#define EMAC_QSERDES_COM_SYSCLK_EN_SEL 0x000038
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#define EMAC_QSERDES_COM_RESETSM_CNTRL 0x000040
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#define EMAC_QSERDES_COM_PLLLOCK_CMP1 0x000044
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#define EMAC_QSERDES_COM_PLLLOCK_CMP2 0x000048
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#define EMAC_QSERDES_COM_PLLLOCK_CMP3 0x00004c
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#define EMAC_QSERDES_COM_PLLLOCK_CMP_EN 0x000050
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#define EMAC_QSERDES_COM_BGTC 0x000058
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#define EMAC_QSERDES_COM_DEC_START1 0x000064
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#define EMAC_QSERDES_COM_RES_TRIM_SEARCH 0x000088
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#define EMAC_QSERDES_COM_DIV_FRAC_START1 0x000098
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#define EMAC_QSERDES_COM_DIV_FRAC_START2 0x00009c
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#define EMAC_QSERDES_COM_DIV_FRAC_START3 0x0000a0
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#define EMAC_QSERDES_COM_DEC_START2 0x0000a4
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#define EMAC_QSERDES_COM_PLL_CRCTRL 0x0000ac
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#define EMAC_QSERDES_COM_RESET_SM 0x0000bc
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#define EMAC_QSERDES_TX_BIST_MODE_LANENO 0x000100
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#define EMAC_QSERDES_TX_TX_EMP_POST1_LVL 0x000108
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#define EMAC_QSERDES_TX_TX_DRV_LVL 0x00010c
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#define EMAC_QSERDES_TX_LANE_MODE 0x000150
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#define EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN 0x000170
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#define EMAC_QSERDES_RX_CDR_CONTROL 0x000200
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#define EMAC_QSERDES_RX_CDR_CONTROL2 0x000210
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#define EMAC_QSERDES_RX_RX_EQ_GAIN12 0x000230
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/* EMAC_SGMII register offsets */
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#define EMAC_SGMII_PHY_SERDES_START 0x000300
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#define EMAC_SGMII_PHY_CMN_PWR_CTRL 0x000304
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#define EMAC_SGMII_PHY_RX_PWR_CTRL 0x000308
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#define EMAC_SGMII_PHY_TX_PWR_CTRL 0x00030C
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#define EMAC_SGMII_PHY_LANE_CTRL1 0x000318
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#define EMAC_SGMII_PHY_AUTONEG_CFG2 0x000348
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#define EMAC_SGMII_PHY_CDR_CTRL0 0x000358
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#define EMAC_SGMII_PHY_SPEED_CFG1 0x000374
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#define EMAC_SGMII_PHY_POW_DWN_CTRL0 0x000380
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#define EMAC_SGMII_PHY_RESET_CTRL 0x0003a8
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#define EMAC_SGMII_PHY_IRQ_CMD 0x0003ac
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#define EMAC_SGMII_PHY_INTERRUPT_CLEAR 0x0003b0
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#define EMAC_SGMII_PHY_INTERRUPT_MASK 0x0003b4
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#define EMAC_SGMII_PHY_INTERRUPT_STATUS 0x0003b8
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#define EMAC_SGMII_PHY_RX_CHK_STATUS 0x0003d4
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#define EMAC_SGMII_PHY_AUTONEG0_STATUS 0x0003e0
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#define EMAC_SGMII_PHY_AUTONEG1_STATUS 0x0003e4
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#define SGMII_CDR_MAX_CNT 0x0f
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#define QSERDES_PLL_IPSETI_DEF 0x01
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#define QSERDES_PLL_IPSETI_MDM 0x03
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#define QSERDES_PLL_CP_SETI 0x3b
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#define QSERDES_PLL_IP_SETP 0x0a
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#define QSERDES_PLL_CP_SETP 0x09
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#define QSERDES_PLL_CRCTRL 0xfb
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#define QSERDES_PLL_DEC 2
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#define QSERDES_PLL_DIV_FRAC_START1 0x55
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#define QSERDES_PLL_DIV_FRAC_START2 0x2a
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#define QSERDES_PLL_DIV_FRAC_START3 0x03
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#define QSERDES_PLL_LOCK_CMP1 0x2b
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#define QSERDES_PLL_LOCK_CMP2 0x68
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#define QSERDES_PLL_LOCK_CMP3 0x00
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#define QSERDES_RX_CDR_CTRL1_THRESH 0x03
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#define QSERDES_RX_CDR_CTRL1_GAIN 0x02
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#define QSERDES_RX_CDR_CTRL2_THRESH 0x03
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#define QSERDES_RX_CDR_CTRL2_GAIN 0x04
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#define QSERDES_RX_EQ_GAIN2 0xf
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#define QSERDES_RX_EQ_GAIN1 0xf
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#define QSERDES_TX_BIST_MODE_LANENO 0x00
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#define QSERDES_TX_DRV_LVL 0x0f
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#define QSERDES_TX_EMP_POST1_LVL 1
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#define QSERDES_TX_LANE_MODE 0x08
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#define SGMII_PHY_IRQ_CLR_WAIT_TIME 10
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#define SGMII_PHY_INTERRUPT_ERR (\
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DECODE_CODE_ERR |\
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DECODE_DISP_ERR)
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#define SGMII_ISR_AN_MASK (\
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AN_REQUEST |\
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AN_START |\
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AN_END |\
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AN_ILLEGAL_TERM |\
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PLL_UNLOCK |\
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SYNC_FAIL)
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#define SGMII_ISR_MASK (\
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SGMII_PHY_INTERRUPT_ERR |\
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SGMII_ISR_AN_MASK)
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/* SGMII TX_CONFIG */
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#define TXCFG_LINK 0x8000
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#define TXCFG_MODE_BMSK 0x1c00
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#define TXCFG_1000_FULL 0x1800
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#define TXCFG_100_FULL 0x1400
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#define TXCFG_100_HALF 0x0400
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#define TXCFG_10_FULL 0x1000
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#define TXCFG_10_HALF 0x0000
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#define SERDES_START_WAIT_TIMES 100
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struct emac_sgmii {
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void __iomem *base;
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/* Points to digital part of the per lane base address */
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void __iomem *laned;
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int irq;
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};
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int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt);
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int emac_sgmii_link_check_no_ephy(struct emac_adapter *adpt, u32 *speed,
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bool *link_up);
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int emac_hw_clear_sgmii_intr_status(struct emac_adapter *adpt, u32 irq_bits);
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int emac_sgmii_up(struct emac_adapter *adpt);
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int emac_sgmii_autoneg_check(struct emac_adapter *adpt, u32 *speed,
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bool *link_up);
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int emac_sgmii_init_ephy_nop(struct emac_adapter *adpt);
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int emac_sgmii_v1_init_link(struct emac_adapter *adpt, u32 speed, bool autoneg,
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bool fc);
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int emac_sgmii_init_link(struct emac_adapter *adpt, u32 speed, bool autoneg,
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bool fc);
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void emac_sgmii_reset_prepare(struct emac_adapter *adpt);
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void emac_sgmii_down(struct emac_adapter *adpt);
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void emac_sgmii_tx_clk_set_rate_nop(struct emac_adapter *adpt);
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void emac_sgmii_periodic_check(struct emac_adapter *adpt);
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irqreturn_t emac_sgmii_isr(int _irq, void *data);
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#endif /*_EMAC_SGMII_H_*/
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