403 lines
13 KiB
C
403 lines
13 KiB
C
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/*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __QPIC_NAND_H
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#define __QPIC_NAND_H
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/crc16.h>
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#include <linux/bitrev.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/ctype.h>
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#include <linux/msm-sps.h>
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#include <linux/msm-bus.h>
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#include <soc/qcom/smem.h>
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#define PAGE_SIZE_2K 2048
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#define PAGE_SIZE_4K 4096
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#undef WRITE /* To avoid redefinition in above header files */
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#define WRITE 1
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#define READ 0
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#define MSM_NAND_IDLE_TIMEOUT 200 /* msecs */
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#define MSM_NAND_BUS_VOTE_MAX_RATE 100000000 /* Hz */
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/*
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* The maximum no of descriptors per transfer (page read/write) won't be more
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* than 64. For more details on what those commands are, please refer to the
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* page read and page write functions in the driver.
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*/
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#define SPS_MAX_DESC_NUM 64
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#define SPS_DATA_CONS_PIPE_INDEX 0
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#define SPS_DATA_PROD_PIPE_INDEX 1
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#define SPS_CMD_CONS_PIPE_INDEX 2
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#define msm_virt_to_dma(chip, vaddr) \
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((chip)->dma_phys_addr + \
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((uint8_t *)(vaddr) - (chip)->dma_virt_addr))
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/*
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* A single page read/write request would typically need DMA memory of about
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* 1K memory approximately. So for a single request this memory is more than
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* enough.
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*
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* But to accommodate multiple clients we allocate 8K of memory. Though only
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* one client request can be submitted to NANDc at any time, other clients can
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* still prepare the descriptors while waiting for current client request to
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* be done. Thus for a total memory of 8K, the driver can currently support
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* maximum clients up to 7 or 8 at a time. The client for which there is no
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* free DMA memory shall wait on the wait queue until other clients free up
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* the required memory.
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*/
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#define MSM_NAND_DMA_BUFFER_SIZE SZ_8K
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/*
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* This defines the granularity at which the buffer management is done. The
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* total number of slots is based on the size of the atomic_t variable
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* dma_buffer_busy(number of bits) within the structure msm_nand_chip.
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*/
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#define MSM_NAND_DMA_BUFFER_SLOT_SZ \
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(MSM_NAND_DMA_BUFFER_SIZE / (sizeof(((atomic_t *)0)->counter) * 8))
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/* ONFI(Open NAND Flash Interface) parameters */
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#define MSM_NAND_CFG0_RAW_ONFI_IDENTIFIER 0x88000800
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#define MSM_NAND_CFG0_RAW_ONFI_PARAM_INFO 0x88040000
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#define MSM_NAND_CFG1_RAW_ONFI_IDENTIFIER 0x0005045d
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#define MSM_NAND_CFG1_RAW_ONFI_PARAM_INFO 0x0005045d
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#define ONFI_PARAM_INFO_LENGTH 0x0200
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#define ONFI_PARAM_PAGE_LENGTH 0x0100
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#define ONFI_PARAMETER_PAGE_SIGNATURE 0x49464E4F
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#define FLASH_READ_ONFI_SIGNATURE_ADDRESS 0x20
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#define FLASH_READ_ONFI_PARAMETERS_COMMAND 0xEC
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#define FLASH_READ_ONFI_PARAMETERS_ADDRESS 0x00
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#define FLASH_READ_DEVICE_ID_ADDRESS 0x00
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#define MSM_NAND_RESET_FLASH_STS 0x00000020
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#define MSM_NAND_RESET_READ_STS 0x000000C0
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/* QPIC NANDc (NAND Controller) Register Set */
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#define MSM_NAND_REG(info, off) (info->nand_phys + off)
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#define MSM_NAND_QPIC_VERSION(info) MSM_NAND_REG(info, 0x24100)
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#define MSM_NAND_FLASH_CMD(info) MSM_NAND_REG(info, 0x30000)
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#define MSM_NAND_ADDR0(info) MSM_NAND_REG(info, 0x30004)
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#define MSM_NAND_ADDR1(info) MSM_NAND_REG(info, 0x30008)
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#define MSM_NAND_EXEC_CMD(info) MSM_NAND_REG(info, 0x30010)
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#define MSM_NAND_FLASH_STATUS(info) MSM_NAND_REG(info, 0x30014)
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#define FS_OP_ERR (1 << 4)
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#define FS_MPU_ERR (1 << 8)
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#define FS_DEVICE_STS_ERR (1 << 16)
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#define FS_DEVICE_WP (1 << 23)
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#define MSM_NAND_BUFFER_STATUS(info) MSM_NAND_REG(info, 0x30018)
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#define BS_UNCORRECTABLE_BIT (1 << 8)
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#define BS_CORRECTABLE_ERR_MSK 0x1F
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#define MSM_NAND_DEV0_CFG0(info) MSM_NAND_REG(info, 0x30020)
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#define DISABLE_STATUS_AFTER_WRITE 4
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#define CW_PER_PAGE 6
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#define UD_SIZE_BYTES 9
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#define SPARE_SIZE_BYTES 23
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#define NUM_ADDR_CYCLES 27
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#define MSM_NAND_DEV0_CFG1(info) MSM_NAND_REG(info, 0x30024)
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#define DEV0_CFG1_ECC_DISABLE 0
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#define WIDE_FLASH 1
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#define NAND_RECOVERY_CYCLES 2
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#define CS_ACTIVE_BSY 5
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#define BAD_BLOCK_BYTE_NUM 6
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#define BAD_BLOCK_IN_SPARE_AREA 16
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#define WR_RD_BSY_GAP 17
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#define ENABLE_BCH_ECC 27
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#define BYTES_512 512
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#define BYTES_516 516
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#define BYTES_517 517
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#define MSM_NAND_DEV0_ECC_CFG(info) MSM_NAND_REG(info, 0x30028)
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#define ECC_CFG_ECC_DISABLE 0
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#define ECC_SW_RESET 1
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#define ECC_MODE 4
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#define ECC_PARITY_SIZE_BYTES 8
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#define ECC_NUM_DATA_BYTES 16
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#define ECC_FORCE_CLK_OPEN 30
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#define MSM_NAND_READ_ID(info) MSM_NAND_REG(info, 0x30040)
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#define MSM_NAND_READ_STATUS(info) MSM_NAND_REG(info, 0x30044)
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#define MSM_NAND_READ_ID2(info) MSM_NAND_REG(info, 0x30048)
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#define EXTENDED_FETCH_ID BIT(19)
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#define MSM_NAND_DEV_CMD1(info) MSM_NAND_REG(info, 0x300A4)
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#define MSM_NAND_DEV_CMD_VLD(info) MSM_NAND_REG(info, 0x300AC)
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#define MSM_NAND_EBI2_ECC_BUF_CFG(info) MSM_NAND_REG(info, 0x300F0)
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#define MSM_NAND_ERASED_CW_DETECT_CFG(info) MSM_NAND_REG(info, 0x300E8)
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#define ERASED_CW_ECC_MASK 1
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#define AUTO_DETECT_RES 0
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#define MASK_ECC (1 << ERASED_CW_ECC_MASK)
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#define RESET_ERASED_DET (1 << AUTO_DETECT_RES)
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#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
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#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
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#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
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#define MSM_NAND_ERASED_CW_DETECT_STATUS(info) MSM_NAND_REG(info, 0x300EC)
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#define PAGE_ALL_ERASED 7
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#define CODEWORD_ALL_ERASED 6
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#define PAGE_ERASED 5
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#define CODEWORD_ERASED 4
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#define ERASED_PAGE ((1 << PAGE_ALL_ERASED) | (1 << PAGE_ERASED))
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#define ERASED_CW ((1 << CODEWORD_ALL_ERASED) | (1 << CODEWORD_ERASED))
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#define MSM_NAND_CTRL(info) MSM_NAND_REG(info, 0x30F00)
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#define BAM_MODE_EN 0
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#define MSM_NAND_VERSION(info) MSM_NAND_REG(info, 0x34F08)
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#define MSM_NAND_READ_LOCATION_0(info) MSM_NAND_REG(info, 0x30F20)
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#define MSM_NAND_READ_LOCATION_1(info) MSM_NAND_REG(info, 0x30F24)
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/* device commands */
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#define MSM_NAND_CMD_PAGE_READ 0x32
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#define MSM_NAND_CMD_PAGE_READ_ECC 0x33
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#define MSM_NAND_CMD_PAGE_READ_ALL 0x34
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#define MSM_NAND_CMD_PRG_PAGE 0x36
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#define MSM_NAND_CMD_PRG_PAGE_ECC 0x37
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#define MSM_NAND_CMD_PRG_PAGE_ALL 0x39
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#define MSM_NAND_CMD_BLOCK_ERASE 0x3A
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#define MSM_NAND_CMD_FETCH_ID 0x0B
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/* Version Mask */
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#define MSM_NAND_VERSION_MAJOR_MASK 0xF0000000
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#define MSM_NAND_VERSION_MAJOR_SHIFT 28
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#define MSM_NAND_VERSION_MINOR_MASK 0x0FFF0000
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#define MSM_NAND_VERSION_MINOR_SHIFT 16
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#define CMD SPS_IOVEC_FLAG_CMD
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#define CMD_LCK (CMD | SPS_IOVEC_FLAG_LOCK)
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#define INT SPS_IOVEC_FLAG_INT
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#define INT_UNLCK (INT | SPS_IOVEC_FLAG_UNLOCK)
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#define CMD_INT_UNLCK (CMD | INT_UNLCK)
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#define NWD SPS_IOVEC_FLAG_NWD
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/* Structure that defines a NAND SPS command element */
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struct msm_nand_sps_cmd {
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struct sps_command_element ce;
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uint32_t flags;
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};
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struct msm_nand_cmd_setup_desc {
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struct sps_command_element ce[11];
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uint32_t flags;
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uint32_t num_ce;
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};
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struct msm_nand_cmd_cw_desc {
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struct sps_command_element ce[3];
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uint32_t flags;
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uint32_t num_ce;
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};
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struct msm_nand_rw_cmd_desc {
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uint32_t count;
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struct msm_nand_cmd_setup_desc setup_desc;
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struct msm_nand_cmd_cw_desc cw_desc[];
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};
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/*
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* Structure that defines the NAND controller properties as per the
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* NAND flash device/chip that is attached.
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*/
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struct msm_nand_chip {
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struct device *dev;
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/*
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* DMA memory will be allocated only once during probe and this memory
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* will be used by all NAND clients. This wait queue is needed to
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* make the applications wait for DMA memory to be free'd when the
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* complete memory is exhausted.
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*/
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wait_queue_head_t dma_wait_queue;
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atomic_t dma_buffer_busy;
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uint8_t *dma_virt_addr;
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dma_addr_t dma_phys_addr;
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uint32_t ecc_parity_bytes;
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uint32_t bch_caps; /* Controller BCH ECC capabilities */
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#define MSM_NAND_CAP_4_BIT_BCH (1 << 0)
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#define MSM_NAND_CAP_8_BIT_BCH (1 << 1)
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uint32_t cw_size;
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/* NANDc register configurations */
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uint32_t cfg0, cfg1, cfg0_raw, cfg1_raw;
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uint32_t ecc_buf_cfg;
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uint32_t ecc_bch_cfg;
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uint32_t ecc_cfg_raw;
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};
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/* Structure that defines an SPS end point for a NANDc BAM pipe. */
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struct msm_nand_sps_endpt {
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struct sps_pipe *handle;
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struct sps_connect config;
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struct sps_register_event event;
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struct completion completion;
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uint32_t index;
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};
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/*
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* Structure that defines NANDc SPS data - BAM handle and an end point
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* for each BAM pipe.
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*/
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struct msm_nand_sps_info {
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unsigned long bam_handle;
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struct msm_nand_sps_endpt data_prod;
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struct msm_nand_sps_endpt data_cons;
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struct msm_nand_sps_endpt cmd_pipe;
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};
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/*
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* Structure that contains flash device information. This gets updated after
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* the NAND flash device detection.
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*/
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struct flash_identification {
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uint32_t flash_id;
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uint64_t density;
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uint32_t widebus;
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uint32_t pagesize;
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uint32_t blksize;
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uint32_t oobsize;
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uint32_t ecc_correctability;
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uint32_t ecc_capability; /* Set based on the ECC capability selected. */
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};
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struct msm_nand_clk_data {
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struct clk *qpic_clk;
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struct msm_bus_scale_pdata *use_cases;
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uint32_t client_handle;
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atomic_t clk_enabled;
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atomic_t curr_vote;
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};
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/* Structure that defines NANDc private data. */
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struct msm_nand_info {
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struct mtd_info mtd;
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struct msm_nand_chip nand_chip;
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struct msm_nand_sps_info sps;
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unsigned long bam_phys;
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unsigned long nand_phys;
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void __iomem *bam_base;
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int bam_irq;
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/*
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* This lock must be acquired before submitting any command or data
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* descriptors to BAM pipes and must be held until all the submitted
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* descriptors are processed.
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*
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* This is required to ensure that both command and descriptors are
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* submitted atomically without interruption from other clients,
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* when there are requests from more than client at any time.
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* Othewise, data and command descriptors can be submitted out of
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* order for a request which can cause data corruption.
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*/
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struct mutex lock;
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struct flash_identification flash_dev;
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struct msm_nand_clk_data clk_data;
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u64 dma_mask;
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};
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/* Structure that defines an ONFI parameter page (512B) */
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struct onfi_param_page {
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uint32_t parameter_page_signature;
|
||
|
|
uint16_t revision_number;
|
||
|
|
uint16_t features_supported;
|
||
|
|
uint16_t optional_commands_supported;
|
||
|
|
uint8_t reserved0[22];
|
||
|
|
uint8_t device_manufacturer[12];
|
||
|
|
uint8_t device_model[20];
|
||
|
|
uint8_t jedec_manufacturer_id;
|
||
|
|
uint16_t date_code;
|
||
|
|
uint8_t reserved1[13];
|
||
|
|
uint32_t number_of_data_bytes_per_page;
|
||
|
|
uint16_t number_of_spare_bytes_per_page;
|
||
|
|
uint32_t number_of_data_bytes_per_partial_page;
|
||
|
|
uint16_t number_of_spare_bytes_per_partial_page;
|
||
|
|
uint32_t number_of_pages_per_block;
|
||
|
|
uint32_t number_of_blocks_per_logical_unit;
|
||
|
|
uint8_t number_of_logical_units;
|
||
|
|
uint8_t number_of_address_cycles;
|
||
|
|
uint8_t number_of_bits_per_cell;
|
||
|
|
uint16_t maximum_bad_blocks_per_logical_unit;
|
||
|
|
uint16_t block_endurance;
|
||
|
|
uint8_t guaranteed_valid_begin_blocks;
|
||
|
|
uint16_t guaranteed_valid_begin_blocks_endurance;
|
||
|
|
uint8_t number_of_programs_per_page;
|
||
|
|
uint8_t partial_program_attributes;
|
||
|
|
uint8_t number_of_bits_ecc_correctability;
|
||
|
|
uint8_t number_of_interleaved_address_bits;
|
||
|
|
uint8_t interleaved_operation_attributes;
|
||
|
|
uint8_t reserved2[13];
|
||
|
|
uint8_t io_pin_capacitance;
|
||
|
|
uint16_t timing_mode_support;
|
||
|
|
uint16_t program_cache_timing_mode_support;
|
||
|
|
uint16_t maximum_page_programming_time;
|
||
|
|
uint16_t maximum_block_erase_time;
|
||
|
|
uint16_t maximum_page_read_time;
|
||
|
|
uint16_t maximum_change_column_setup_time;
|
||
|
|
uint8_t reserved3[23];
|
||
|
|
uint16_t vendor_specific_revision_number;
|
||
|
|
uint8_t vendor_specific[88];
|
||
|
|
uint16_t integrity_crc;
|
||
|
|
} __attribute__((__packed__));
|
||
|
|
|
||
|
|
#define FLASH_PART_MAGIC1 0x55EE73AA
|
||
|
|
#define FLASH_PART_MAGIC2 0xE35EBDDB
|
||
|
|
#define FLASH_PTABLE_V3 3
|
||
|
|
#define FLASH_PTABLE_V4 4
|
||
|
|
#define FLASH_PTABLE_MAX_PARTS_V3 16
|
||
|
|
#define FLASH_PTABLE_MAX_PARTS_V4 32
|
||
|
|
#define FLASH_PTABLE_HDR_LEN (4*sizeof(uint32_t))
|
||
|
|
#define FLASH_PTABLE_ENTRY_NAME_SIZE 16
|
||
|
|
|
||
|
|
struct flash_partition_entry {
|
||
|
|
char name[FLASH_PTABLE_ENTRY_NAME_SIZE];
|
||
|
|
u32 offset; /* Offset in blocks from beginning of device */
|
||
|
|
u32 length; /* Length of the partition in blocks */
|
||
|
|
u8 attr; /* Flags for this partition */
|
||
|
|
};
|
||
|
|
|
||
|
|
struct flash_partition_table {
|
||
|
|
u32 magic1;
|
||
|
|
u32 magic2;
|
||
|
|
u32 version;
|
||
|
|
u32 numparts;
|
||
|
|
struct flash_partition_entry part_entry[FLASH_PTABLE_MAX_PARTS_V4];
|
||
|
|
};
|
||
|
|
|
||
|
|
#ifdef CONFIG_MSM_SMD
|
||
|
|
static struct flash_partition_table ptable;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static struct mtd_partition mtd_part[FLASH_PTABLE_MAX_PARTS_V4];
|
||
|
|
|
||
|
|
static inline bool is_buffer_in_page(const void *buf, size_t len)
|
||
|
|
{
|
||
|
|
return !(((unsigned long) buf & ~PAGE_MASK) + len > PAGE_SIZE);
|
||
|
|
}
|
||
|
|
#endif /* __QPIC_NAND_H */
|