2024-09-09 08:57:42 +00:00
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/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
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2024-09-09 08:52:07 +00:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <linux/clk.h>
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#include <linux/of_coresight.h>
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#include <linux/coresight.h>
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#include <linux/regulator/consumer.h>
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#include <linux/gpio.h>
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#include <linux/of_gpio.h>
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2024-09-09 08:57:42 +00:00
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#include <linux/pinctrl/consumer.h>
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2024-09-09 08:52:07 +00:00
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#include "coresight-priv.h"
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2024-09-09 08:57:42 +00:00
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#include "coresight-nidnt.h"
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2024-09-09 08:52:07 +00:00
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#define tpiu_writel(drvdata, val, off) __raw_writel((val), drvdata->base + off)
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#define tpiu_readl(drvdata, off) __raw_readl(drvdata->base + off)
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#define TPIU_LOCK(drvdata) \
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do { \
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mb(); \
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tpiu_writel(drvdata, 0x0, CORESIGHT_LAR); \
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} while (0)
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#define TPIU_UNLOCK(drvdata) \
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do { \
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tpiu_writel(drvdata, CORESIGHT_UNLOCK, CORESIGHT_LAR); \
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mb(); \
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} while (0)
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#define TPIU_SUPP_PORTSZ (0x000)
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#define TPIU_CURR_PORTSZ (0x004)
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#define TPIU_SUPP_TRIGMODES (0x100)
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#define TPIU_TRIG_CNTRVAL (0x104)
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#define TPIU_TRIG_MULT (0x108)
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#define TPIU_SUPP_TESTPATM (0x200)
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#define TPIU_CURR_TESTPATM (0x204)
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#define TPIU_TEST_PATREPCNTR (0x208)
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#define TPIU_FFSR (0x300)
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#define TPIU_FFCR (0x304)
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#define TPIU_FSYNC_CNTR (0x308)
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#define TPIU_EXTCTL_INPORT (0x400)
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#define TPIU_EXTCTL_OUTPORT (0x404)
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#define TPIU_ITTRFLINACK (0xEE4)
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#define TPIU_ITTRFLIN (0xEE8)
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#define TPIU_ITATBDATA0 (0xEEC)
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#define TPIU_ITATBCTR2 (0xEF0)
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#define TPIU_ITATBCTR1 (0xEF4)
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#define TPIU_ITATBCTR0 (0xEF8)
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2024-09-09 08:57:42 +00:00
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#define TLMM_SDC2_HDRV_PULL_CTL (0X48)
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#define TLMM_ETM_MODE (0X14)
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2024-09-09 08:52:07 +00:00
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enum tpiu_out_mode {
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TPIU_OUT_MODE_NONE,
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TPIU_OUT_MODE_MICTOR,
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2024-09-09 08:57:42 +00:00
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TPIU_OUT_MODE_SDC_TRACE,
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TPIU_OUT_MODE_SDC_SWDUART,
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TPIU_OUT_MODE_SDC_SWDTRC,
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TPIU_OUT_MODE_SDC_JTAG,
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TPIU_OUT_MODE_SDC_SPMI,
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2024-09-09 08:52:07 +00:00
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};
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enum tpiu_set {
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TPIU_SET_NONE,
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TPIU_SET_A,
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TPIU_SET_B,
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};
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struct tpiu_drvdata {
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void __iomem *base;
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struct device *dev;
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struct coresight_device *csdev;
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struct clk *clk;
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struct mutex mutex;
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enum tpiu_out_mode out_mode;
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struct regulator *reg;
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unsigned int reg_low;
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unsigned int reg_high;
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unsigned int reg_lpm;
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unsigned int reg_hpm;
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2024-09-09 08:57:42 +00:00
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struct regulator *reg_io;
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unsigned int reg_low_io;
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unsigned int reg_high_io;
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unsigned int reg_lpm_io;
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unsigned int reg_hpm_io;
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2024-09-09 08:52:07 +00:00
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enum tpiu_set set;
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2024-09-09 08:57:42 +00:00
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struct pinctrl *tpiu_pctrl;
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2024-09-09 08:52:07 +00:00
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bool enable;
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2024-09-09 08:57:42 +00:00
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bool nidntsw;
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bool nidnthw; /* Can support nidnt ps sequence */
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bool nidnt_swduart;
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bool nidnt_swdtrc;
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bool nidnt_jtag;
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bool nidnt_spmi;
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};
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static const char * const str_tpiu_out_mode[] = {
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[TPIU_OUT_MODE_NONE] = "none",
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[TPIU_OUT_MODE_MICTOR] = "mictor",
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[TPIU_OUT_MODE_SDC_TRACE] = "sdc",
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[TPIU_OUT_MODE_SDC_SWDUART] = "swduart",
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[TPIU_OUT_MODE_SDC_SWDTRC] = "swdtrc",
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[TPIU_OUT_MODE_SDC_JTAG] = "jtag",
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[TPIU_OUT_MODE_SDC_SPMI] = "spmi",
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2024-09-09 08:52:07 +00:00
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};
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2024-09-09 08:57:42 +00:00
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static int nidnt_boot_hw_detect;
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module_param_named(nidnt_boot_hw_detect,
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nidnt_boot_hw_detect, int, S_IRUGO | S_IWUSR | S_IWGRP);
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static void __tpiu_disable(struct tpiu_drvdata *drvdata);
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static void __tpiu_disable_to_sdc(struct tpiu_drvdata *drvdata);
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2024-09-09 08:52:07 +00:00
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static void tpiu_flush_and_stop(struct tpiu_drvdata *drvdata)
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{
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int count;
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uint32_t ffcr;
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ffcr = tpiu_readl(drvdata, TPIU_FFCR);
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ffcr |= BIT(12);
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tpiu_writel(drvdata, ffcr, TPIU_FFCR);
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ffcr |= BIT(6);
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tpiu_writel(drvdata, ffcr, TPIU_FFCR);
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/* Ensure flush completes */
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for (count = TIMEOUT_US; BVAL(tpiu_readl(drvdata, TPIU_FFCR), 6) != 0
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&& count > 0; count--)
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udelay(1);
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WARN(count == 0, "timeout while flushing TPIU, TPIU_FFCR: %#x\n",
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tpiu_readl(drvdata, TPIU_FFCR));
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}
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2024-09-09 08:57:42 +00:00
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static void __tpiu_enable(struct tpiu_drvdata *drvdata, uint32_t portsz,
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uint32_t ffcr)
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{
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TPIU_UNLOCK(drvdata);
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tpiu_writel(drvdata, portsz, TPIU_CURR_PORTSZ);
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tpiu_writel(drvdata, ffcr, TPIU_FFCR);
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TPIU_LOCK(drvdata);
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}
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2024-09-09 08:52:07 +00:00
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static int __tpiu_enable_seta(struct tpiu_drvdata *drvdata)
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{
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2024-09-09 08:57:42 +00:00
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int ret;
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struct pinctrl *pctrl;
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struct pinctrl_state *seta_pctrl;
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2024-09-09 08:52:07 +00:00
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2024-09-09 08:57:42 +00:00
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pctrl = devm_pinctrl_get(drvdata->dev);
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if (IS_ERR(pctrl)) {
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dev_err(drvdata->dev, "pinctrl handle failed for seta\n");
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return PTR_ERR(pctrl);
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}
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2024-09-09 08:52:07 +00:00
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2024-09-09 08:57:42 +00:00
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seta_pctrl = pinctrl_lookup_state(pctrl, "seta-pctrl");
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if (IS_ERR(seta_pctrl)) {
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dev_err(drvdata->dev,
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"pinctrl get state failed for seta\n");
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ret = PTR_ERR(seta_pctrl);
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goto err;
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2024-09-09 08:52:07 +00:00
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}
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2024-09-09 08:57:42 +00:00
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ret = pinctrl_select_state(pctrl, seta_pctrl);
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if (ret) {
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dev_err(drvdata->dev,
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"pinctrl enable state failed for seta\n");
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goto err;
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2024-09-09 08:52:07 +00:00
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}
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2024-09-09 08:57:42 +00:00
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drvdata->tpiu_pctrl = pctrl;
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return 0;
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err:
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devm_pinctrl_put(pctrl);
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2024-09-09 08:52:07 +00:00
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return ret;
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}
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static int __tpiu_enable_setb(struct tpiu_drvdata *drvdata)
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{
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2024-09-09 08:57:42 +00:00
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int ret;
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struct pinctrl *pctrl;
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struct pinctrl_state *setb_pctrl;
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2024-09-09 08:52:07 +00:00
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2024-09-09 08:57:42 +00:00
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pctrl = devm_pinctrl_get(drvdata->dev);
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if (IS_ERR(pctrl)) {
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dev_err(drvdata->dev, "pinctrl handle failed for setb\n");
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return PTR_ERR(pctrl);
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}
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2024-09-09 08:52:07 +00:00
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2024-09-09 08:57:42 +00:00
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setb_pctrl = pinctrl_lookup_state(pctrl, "setb-pctrl");
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if (IS_ERR(setb_pctrl)) {
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dev_err(drvdata->dev,
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"pinctrl get state failed for setb\n");
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ret = PTR_ERR(setb_pctrl);
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goto err;
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2024-09-09 08:52:07 +00:00
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}
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2024-09-09 08:57:42 +00:00
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ret = pinctrl_select_state(pctrl, setb_pctrl);
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if (ret) {
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dev_err(drvdata->dev,
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"pinctrl enable state failed for setb\n");
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goto err;
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2024-09-09 08:52:07 +00:00
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}
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2024-09-09 08:57:42 +00:00
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drvdata->tpiu_pctrl = pctrl;
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return 0;
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err:
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devm_pinctrl_put(pctrl);
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2024-09-09 08:52:07 +00:00
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return ret;
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}
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static int __tpiu_enable_to_mictor(struct tpiu_drvdata *drvdata)
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{
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int ret;
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if (drvdata->set == TPIU_SET_A) {
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ret = __tpiu_enable_seta(drvdata);
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if (ret)
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return ret;
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} else if (drvdata->set == TPIU_SET_B) {
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ret = __tpiu_enable_setb(drvdata);
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if (ret)
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return ret;
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}
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2024-09-09 08:57:42 +00:00
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__tpiu_enable(drvdata, 0x8000, 0x101);
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2024-09-09 08:52:07 +00:00
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return 0;
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}
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static int tpiu_reg_set_optimum_mode(struct regulator *reg,
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unsigned int reg_hpm)
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{
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if (regulator_count_voltages(reg) <= 0)
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return 0;
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return regulator_set_optimum_mode(reg, reg_hpm);
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}
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static int tpiu_reg_set_voltage(struct regulator *reg, unsigned int reg_low,
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unsigned int reg_high)
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{
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if (regulator_count_voltages(reg) <= 0)
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return 0;
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return regulator_set_voltage(reg, reg_low, reg_high);
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}
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static int __tpiu_enable_to_sdc(struct tpiu_drvdata *drvdata)
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{
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int ret;
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2024-09-09 08:57:42 +00:00
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if (!drvdata->nidntsw && !drvdata->nidnthw)
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return -EINVAL;
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if (!drvdata->reg || !drvdata->reg_io)
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2024-09-09 08:52:07 +00:00
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return -EINVAL;
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ret = tpiu_reg_set_optimum_mode(drvdata->reg, drvdata->reg_hpm);
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if (ret < 0)
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return ret;
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ret = tpiu_reg_set_voltage(drvdata->reg, drvdata->reg_low,
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drvdata->reg_high);
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if (ret)
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goto err0;
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ret = regulator_enable(drvdata->reg);
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if (ret)
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goto err1;
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2024-09-09 08:57:42 +00:00
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ret = tpiu_reg_set_optimum_mode(drvdata->reg_io, drvdata->reg_hpm_io);
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if (ret < 0)
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goto err2;
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ret = tpiu_reg_set_voltage(drvdata->reg_io, drvdata->reg_low_io,
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drvdata->reg_high_io);
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if (ret)
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goto err3;
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ret = regulator_enable(drvdata->reg_io);
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if (ret)
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goto err4;
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2024-09-09 08:52:07 +00:00
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2024-09-09 08:57:42 +00:00
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ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_FIXED);
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if (ret)
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goto err5;
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2024-09-09 08:52:07 +00:00
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2024-09-09 08:57:42 +00:00
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return 0;
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err5:
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regulator_disable(drvdata->reg_io);
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err4:
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tpiu_reg_set_voltage(drvdata->reg_io, 0, drvdata->reg_high_io);
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err3:
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tpiu_reg_set_optimum_mode(drvdata->reg_io, 0);
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err2:
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regulator_disable(drvdata->reg);
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err1:
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tpiu_reg_set_voltage(drvdata->reg, 0, drvdata->reg_high);
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err0:
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tpiu_reg_set_optimum_mode(drvdata->reg, 0);
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return ret;
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}
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2024-09-09 08:52:07 +00:00
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2024-09-09 08:57:42 +00:00
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static int __tpiu_enable_to_sdc_trace(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
int ret;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
ret = __tpiu_enable_to_sdc(drvdata);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
__tpiu_enable(drvdata, 0x8, 0x103);
|
|
|
|
|
|
|
|
if (drvdata->nidnthw) {
|
|
|
|
ret = coresight_nidnt_config_qdsd_enable(true);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
ret = coresight_nidnt_config_swoverride(NIDNT_MODE_SDC_TRACE);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
} else {
|
|
|
|
coresight_nidnt_writel(0x16D, TLMM_SDC2_HDRV_PULL_CTL);
|
|
|
|
coresight_nidnt_writel(1, TLMM_ETM_MODE);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
__tpiu_disable(drvdata);
|
|
|
|
__tpiu_disable_to_sdc(drvdata);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __tpiu_enable_to_sdc_swduart(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Vote for clk on since tracing may or may not be enabled in
|
|
|
|
* swduart mode and hence the clk is not guaranteed to be enabled.
|
|
|
|
*/
|
|
|
|
ret = clk_prepare_enable(drvdata->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
ret = __tpiu_enable_to_sdc(drvdata);
|
|
|
|
if (ret)
|
|
|
|
goto err0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Required sequence to prevent SRST asserstion: set trace to
|
|
|
|
* continuous mode followed by setting ETM MODE to 1 before switching
|
|
|
|
* to swd.
|
|
|
|
*/
|
|
|
|
__tpiu_enable(drvdata, 0x8, 0x103);
|
|
|
|
|
|
|
|
if (drvdata->nidnthw) {
|
|
|
|
ret = coresight_nidnt_config_qdsd_enable(true);
|
|
|
|
if (ret)
|
|
|
|
goto err1;
|
|
|
|
|
|
|
|
ret = coresight_nidnt_config_swoverride(NIDNT_MODE_SDC_SWDUART);
|
|
|
|
if (ret)
|
|
|
|
goto err1;
|
|
|
|
} else {
|
|
|
|
coresight_nidnt_writel(1, TLMM_ETM_MODE);
|
|
|
|
/* Pull down sdc cmd line */
|
|
|
|
coresight_nidnt_writel(0x96D, TLMM_SDC2_HDRV_PULL_CTL);
|
|
|
|
coresight_nidnt_writel(2, TLMM_ETM_MODE);
|
|
|
|
}
|
2024-09-09 08:52:07 +00:00
|
|
|
return 0;
|
|
|
|
err1:
|
2024-09-09 08:57:42 +00:00
|
|
|
__tpiu_disable(drvdata);
|
|
|
|
__tpiu_disable_to_sdc(drvdata);
|
2024-09-09 08:52:07 +00:00
|
|
|
err0:
|
2024-09-09 08:57:42 +00:00
|
|
|
clk_disable_unprepare(drvdata->clk);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __tpiu_enable_to_sdc_swdtrc(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Vote for clk on since tracing may or may not be enabled in
|
|
|
|
* swdtrc mode and hence the clk is not guaranteed to be enabled.
|
|
|
|
*/
|
|
|
|
ret = clk_prepare_enable(drvdata->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = __tpiu_enable_to_sdc(drvdata);
|
|
|
|
if (ret)
|
|
|
|
goto err0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Required sequence to prevent SRST asserstion: set trace to
|
|
|
|
* continuous mode followed by setting ETM MODE to 1 before switching
|
|
|
|
* to swd.
|
|
|
|
*/
|
|
|
|
__tpiu_enable(drvdata, 0x2, 0x103);
|
|
|
|
|
|
|
|
if (drvdata->nidnthw) {
|
|
|
|
ret = coresight_nidnt_config_qdsd_enable(true);
|
|
|
|
if (ret)
|
|
|
|
goto err1;
|
|
|
|
|
|
|
|
ret = coresight_nidnt_config_swoverride(NIDNT_MODE_SDC_SWDTRC);
|
|
|
|
if (ret)
|
|
|
|
goto err1;
|
|
|
|
} else {
|
|
|
|
coresight_nidnt_writel(1, TLMM_ETM_MODE);
|
|
|
|
/* Pull down sdc cmd line */
|
|
|
|
coresight_nidnt_writel(0x96D, TLMM_SDC2_HDRV_PULL_CTL);
|
|
|
|
coresight_nidnt_writel(3, TLMM_ETM_MODE);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
err1:
|
|
|
|
__tpiu_disable(drvdata);
|
|
|
|
__tpiu_disable_to_sdc(drvdata);
|
|
|
|
err0:
|
|
|
|
clk_disable_unprepare(drvdata->clk);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __tpiu_enable_to_sdc_jtag(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = __tpiu_enable_to_sdc(drvdata);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = coresight_nidnt_config_qdsd_enable(true);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
ret = coresight_nidnt_config_swoverride(NIDNT_MODE_SDC_JTAG);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
__tpiu_disable_to_sdc(drvdata);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __tpiu_enable_to_sdc_spmi(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = __tpiu_enable_to_sdc(drvdata);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = coresight_nidnt_config_qdsd_enable(true);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
ret = coresight_nidnt_config_swoverride(NIDNT_MODE_SDC_SPMI);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
__tpiu_disable_to_sdc(drvdata);
|
2024-09-09 08:52:07 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tpiu_enable(struct coresight_device *csdev)
|
|
|
|
{
|
|
|
|
struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(drvdata->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
mutex_lock(&drvdata->mutex);
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
/*
|
|
|
|
* swd modes are enabled when stored in out_mode to allow debugging
|
|
|
|
* in swd modes.
|
|
|
|
*/
|
2024-09-09 08:52:07 +00:00
|
|
|
if (drvdata->out_mode == TPIU_OUT_MODE_MICTOR)
|
|
|
|
ret = __tpiu_enable_to_mictor(drvdata);
|
2024-09-09 08:57:42 +00:00
|
|
|
else if (drvdata->out_mode == TPIU_OUT_MODE_SDC_TRACE)
|
|
|
|
ret = __tpiu_enable_to_sdc_trace(drvdata);
|
2024-09-09 08:52:07 +00:00
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
drvdata->enable = true;
|
|
|
|
|
|
|
|
mutex_unlock(&drvdata->mutex);
|
|
|
|
|
|
|
|
dev_info(drvdata->dev, "TPIU enabled\n");
|
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
mutex_unlock(&drvdata->mutex);
|
|
|
|
clk_disable_unprepare(drvdata->clk);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __tpiu_disable(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
TPIU_UNLOCK(drvdata);
|
|
|
|
|
|
|
|
tpiu_flush_and_stop(drvdata);
|
|
|
|
|
|
|
|
TPIU_LOCK(drvdata);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __tpiu_disable_seta(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
2024-09-09 08:57:42 +00:00
|
|
|
devm_pinctrl_put(drvdata->tpiu_pctrl);
|
2024-09-09 08:52:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __tpiu_disable_setb(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
2024-09-09 08:57:42 +00:00
|
|
|
devm_pinctrl_put(drvdata->tpiu_pctrl);
|
2024-09-09 08:52:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __tpiu_disable_to_mictor(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
2024-09-09 08:57:42 +00:00
|
|
|
/* mictor mode needs to be disbled only when tracing is enabled */
|
|
|
|
if (!drvdata->enable)
|
|
|
|
return;
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
__tpiu_disable(drvdata);
|
|
|
|
|
|
|
|
if (drvdata->set == TPIU_SET_A)
|
|
|
|
__tpiu_disable_seta(drvdata);
|
|
|
|
else if (drvdata->set == TPIU_SET_B)
|
|
|
|
__tpiu_disable_setb(drvdata);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __tpiu_disable_to_sdc(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
2024-09-09 08:57:42 +00:00
|
|
|
if (drvdata->nidntsw)
|
|
|
|
coresight_nidnt_writel(0, TLMM_ETM_MODE);
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE);
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
regulator_disable(drvdata->reg);
|
|
|
|
tpiu_reg_set_voltage(drvdata->reg, 0, drvdata->reg_high);
|
2024-09-09 08:57:42 +00:00
|
|
|
tpiu_reg_set_optimum_mode(drvdata->reg, 0);
|
|
|
|
|
|
|
|
regulator_disable(drvdata->reg_io);
|
|
|
|
tpiu_reg_set_voltage(drvdata->reg_io, 0, drvdata->reg_high_io);
|
|
|
|
tpiu_reg_set_optimum_mode(drvdata->reg_io, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __tpiu_disable_to_sdc_trace(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
/* sdc mode needs to be disabled only when tracing is enabled */
|
|
|
|
if (!drvdata->enable)
|
|
|
|
return;
|
|
|
|
|
|
|
|
__tpiu_disable(drvdata);
|
|
|
|
|
|
|
|
__tpiu_disable_to_sdc(drvdata);
|
|
|
|
|
|
|
|
/* re-enable the nidnt hardware detect */
|
|
|
|
coresight_nidnt_enable_hwdetect();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __tpiu_disable_to_sdc_swduart(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
__tpiu_disable(drvdata);
|
|
|
|
|
|
|
|
__tpiu_disable_to_sdc(drvdata);
|
|
|
|
|
|
|
|
clk_disable_unprepare(drvdata->clk);
|
|
|
|
|
|
|
|
/* re-enable the nidnt hardware detect */
|
|
|
|
coresight_nidnt_enable_hwdetect();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __tpiu_disable_to_sdc_swdtrc(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
__tpiu_disable(drvdata);
|
|
|
|
|
|
|
|
__tpiu_disable_to_sdc(drvdata);
|
|
|
|
|
|
|
|
clk_disable_unprepare(drvdata->clk);
|
|
|
|
|
|
|
|
/* re-enable the nidnt hardware detect */
|
|
|
|
coresight_nidnt_enable_hwdetect();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __tpiu_disable_to_sdc_jtag(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
__tpiu_disable_to_sdc(drvdata);
|
|
|
|
|
|
|
|
/* re-enable the nidnt hardware detect */
|
|
|
|
coresight_nidnt_enable_hwdetect();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __tpiu_disable_to_sdc_spmi(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
__tpiu_disable_to_sdc(drvdata);
|
|
|
|
|
|
|
|
/* re-enable the nidnt hardware detect */
|
|
|
|
coresight_nidnt_enable_hwdetect();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __tpiu_disable_to_out_mode(struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
if (drvdata->out_mode == TPIU_OUT_MODE_MICTOR)
|
|
|
|
__tpiu_disable_to_mictor(drvdata);
|
|
|
|
else if (drvdata->out_mode == TPIU_OUT_MODE_SDC_TRACE)
|
|
|
|
__tpiu_disable_to_sdc_trace(drvdata);
|
|
|
|
else if (drvdata->out_mode == TPIU_OUT_MODE_SDC_SWDUART)
|
|
|
|
__tpiu_disable_to_sdc_swduart(drvdata);
|
|
|
|
else if (drvdata->out_mode == TPIU_OUT_MODE_SDC_SWDTRC)
|
|
|
|
__tpiu_disable_to_sdc_swdtrc(drvdata);
|
|
|
|
else if (drvdata->out_mode == TPIU_OUT_MODE_SDC_JTAG)
|
|
|
|
__tpiu_disable_to_sdc_jtag(drvdata);
|
|
|
|
else if (drvdata->out_mode == TPIU_OUT_MODE_SDC_SPMI)
|
|
|
|
__tpiu_disable_to_sdc_spmi(drvdata);
|
2024-09-09 08:52:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void tpiu_disable(struct coresight_device *csdev)
|
|
|
|
{
|
|
|
|
struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
|
|
|
|
|
|
|
|
mutex_lock(&drvdata->mutex);
|
|
|
|
|
|
|
|
if (drvdata->out_mode == TPIU_OUT_MODE_MICTOR)
|
|
|
|
__tpiu_disable_to_mictor(drvdata);
|
2024-09-09 08:57:42 +00:00
|
|
|
else if (drvdata->out_mode == TPIU_OUT_MODE_SDC_TRACE)
|
|
|
|
__tpiu_disable_to_sdc_trace(drvdata);
|
2024-09-09 08:52:07 +00:00
|
|
|
drvdata->enable = false;
|
|
|
|
|
|
|
|
mutex_unlock(&drvdata->mutex);
|
|
|
|
|
|
|
|
clk_disable_unprepare(drvdata->clk);
|
|
|
|
|
|
|
|
dev_info(drvdata->dev, "TPIU disabled\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tpiu_abort(struct coresight_device *csdev)
|
|
|
|
{
|
|
|
|
struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
|
|
|
|
|
|
|
|
__tpiu_disable(drvdata);
|
|
|
|
|
|
|
|
dev_info(drvdata->dev, "TPIU aborted\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct coresight_ops_sink tpiu_sink_ops = {
|
|
|
|
.enable = tpiu_enable,
|
|
|
|
.disable = tpiu_disable,
|
|
|
|
.abort = tpiu_abort,
|
|
|
|
};
|
|
|
|
|
|
|
|
static ssize_t tpiu_show_out_mode(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct tpiu_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
2024-09-09 08:57:42 +00:00
|
|
|
ssize_t len = 0;
|
|
|
|
uint32_t reg = 0;
|
|
|
|
int i;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
mutex_lock(&drvdata->mutex);
|
|
|
|
|
|
|
|
if (drvdata->nidnthw)
|
|
|
|
reg = coresight_nidnt_get_status();
|
|
|
|
|
|
|
|
if (reg) {
|
|
|
|
/* check mode if nidnthw is enabled */
|
|
|
|
len = scnprintf(buf, PAGE_SIZE, "%s\n",
|
|
|
|
reg == NIDNT_MODE_SDC_SPMI ?
|
|
|
|
"spmi" : (reg ==
|
|
|
|
NIDNT_MODE_SDC_SWDUART ? "swduart" :
|
|
|
|
(reg == NIDNT_MODE_SDC_TRACE ?
|
|
|
|
"trace" : (reg ==
|
|
|
|
NIDNT_MODE_SDC_SWDTRC ? "swdtrc" :
|
|
|
|
(reg == TPIU_OUT_MODE_SDC_JTAG ?
|
|
|
|
"JTAG" : (reg ==
|
|
|
|
NIDNT_MODE_SDCARD ? "sdcard" : "mictor"))))));
|
|
|
|
} else {
|
|
|
|
/* check sw mode when nidnthw is unavailable or disabled */
|
|
|
|
for (i = 0; i < ARRAY_SIZE(str_tpiu_out_mode); i++) {
|
|
|
|
if (drvdata->out_mode == i)
|
|
|
|
len = scnprintf(buf, PAGE_SIZE, "%s\n",
|
|
|
|
str_tpiu_out_mode[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
mutex_unlock(&drvdata->mutex);
|
|
|
|
return len;
|
2024-09-09 08:52:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t tpiu_store_out_mode(struct device *dev,
|
2024-09-09 08:57:42 +00:00
|
|
|
struct device_attribute *attr,
|
|
|
|
const char *buf, size_t size)
|
2024-09-09 08:52:07 +00:00
|
|
|
{
|
|
|
|
struct tpiu_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
char str[10] = "";
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (strlen(buf) >= 10)
|
|
|
|
return -EINVAL;
|
|
|
|
if (sscanf(buf, "%s", str) != 1)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mutex_lock(&drvdata->mutex);
|
2024-09-09 08:57:42 +00:00
|
|
|
|
|
|
|
if (!strcmp(str, str_tpiu_out_mode[TPIU_OUT_MODE_MICTOR])) {
|
2024-09-09 08:52:07 +00:00
|
|
|
if (drvdata->out_mode == TPIU_OUT_MODE_MICTOR)
|
|
|
|
goto out;
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
__tpiu_disable_to_out_mode(drvdata);
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
if (!drvdata->enable) {
|
|
|
|
drvdata->out_mode = TPIU_OUT_MODE_MICTOR;
|
|
|
|
goto out;
|
|
|
|
}
|
2024-09-09 08:57:42 +00:00
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
ret = __tpiu_enable_to_mictor(drvdata);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(drvdata->dev, "failed to enable mictor\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
drvdata->out_mode = TPIU_OUT_MODE_MICTOR;
|
2024-09-09 08:57:42 +00:00
|
|
|
} else if (!strcmp(str, str_tpiu_out_mode[TPIU_OUT_MODE_SDC_TRACE])) {
|
|
|
|
if (drvdata->out_mode == TPIU_OUT_MODE_SDC_TRACE)
|
2024-09-09 08:52:07 +00:00
|
|
|
goto out;
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
__tpiu_disable_to_out_mode(drvdata);
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
if (!drvdata->enable) {
|
2024-09-09 08:57:42 +00:00
|
|
|
drvdata->out_mode = TPIU_OUT_MODE_SDC_TRACE;
|
2024-09-09 08:52:07 +00:00
|
|
|
goto out;
|
|
|
|
}
|
2024-09-09 08:57:42 +00:00
|
|
|
|
|
|
|
ret = __tpiu_enable_to_sdc_trace(drvdata);
|
2024-09-09 08:52:07 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(drvdata->dev, "failed to enable sdc\n");
|
|
|
|
goto err;
|
|
|
|
}
|
2024-09-09 08:57:42 +00:00
|
|
|
drvdata->out_mode = TPIU_OUT_MODE_SDC_TRACE;
|
|
|
|
} else if (!strcmp(str, str_tpiu_out_mode[TPIU_OUT_MODE_SDC_SWDUART])) {
|
|
|
|
if (!drvdata->nidnt_swduart) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (drvdata->out_mode == TPIU_OUT_MODE_SDC_SWDUART)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* Allow enabling swd modes even without tracing enabled */
|
|
|
|
__tpiu_disable_to_out_mode(drvdata);
|
|
|
|
|
|
|
|
ret = __tpiu_enable_to_sdc_swduart(drvdata);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(drvdata->dev, "failed to enable swd uart\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
drvdata->out_mode = TPIU_OUT_MODE_SDC_SWDUART;
|
|
|
|
} else if (!strcmp(str, str_tpiu_out_mode[TPIU_OUT_MODE_SDC_SWDTRC])) {
|
|
|
|
if (!drvdata->nidnt_swdtrc) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (drvdata->out_mode == TPIU_OUT_MODE_SDC_SWDTRC)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* Allow enabling swd modes even without tracing enabled */
|
|
|
|
__tpiu_disable_to_out_mode(drvdata);
|
|
|
|
|
|
|
|
ret = __tpiu_enable_to_sdc_swdtrc(drvdata);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(drvdata->dev, "failed to enable swd trace\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
drvdata->out_mode = TPIU_OUT_MODE_SDC_SWDTRC;
|
|
|
|
} else if (!strcmp(str, str_tpiu_out_mode[TPIU_OUT_MODE_SDC_JTAG])) {
|
|
|
|
if (!drvdata->nidnt_jtag) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (drvdata->out_mode == TPIU_OUT_MODE_SDC_JTAG)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* Allow enabling swd modes even without tracing enabled */
|
|
|
|
__tpiu_disable_to_out_mode(drvdata);
|
|
|
|
|
|
|
|
ret = __tpiu_enable_to_sdc_jtag(drvdata);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(drvdata->dev, "failed to enable JTAG\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
drvdata->out_mode = TPIU_OUT_MODE_SDC_JTAG;
|
|
|
|
} else if (!strcmp(str, str_tpiu_out_mode[TPIU_OUT_MODE_SDC_SPMI])) {
|
|
|
|
if (!drvdata->nidnt_spmi) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (drvdata->out_mode == TPIU_OUT_MODE_SDC_SPMI)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* Allow enabling swd modes even without tracing enabled */
|
|
|
|
__tpiu_disable_to_out_mode(drvdata);
|
|
|
|
|
|
|
|
ret = __tpiu_enable_to_sdc_spmi(drvdata);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(drvdata->dev, "failed to enable spmi\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
drvdata->out_mode = TPIU_OUT_MODE_SDC_SPMI;
|
2024-09-09 08:52:07 +00:00
|
|
|
}
|
2024-09-09 08:57:42 +00:00
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
out:
|
|
|
|
mutex_unlock(&drvdata->mutex);
|
|
|
|
return size;
|
|
|
|
err:
|
|
|
|
mutex_unlock(&drvdata->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR(out_mode, S_IRUGO | S_IWUSR, tpiu_show_out_mode,
|
|
|
|
tpiu_store_out_mode);
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
static ssize_t tpiu_show_available_out_modes(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct tpiu_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
int i;
|
|
|
|
ssize_t len = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(str_tpiu_out_mode); i++) {
|
|
|
|
if ((i == TPIU_OUT_MODE_SDC_SWDTRC && !drvdata->nidnt_swdtrc)
|
|
|
|
|| (i == TPIU_OUT_MODE_SDC_SWDUART && !drvdata->nidnt_swduart)
|
|
|
|
|| (i == TPIU_OUT_MODE_SDC_JTAG && !drvdata->nidnt_jtag)
|
|
|
|
|| (i == TPIU_OUT_MODE_SDC_SPMI && !drvdata->nidnt_spmi))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
len += scnprintf(buf + len, PAGE_SIZE - len, "%s ",
|
|
|
|
str_tpiu_out_mode[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
len += scnprintf(buf + len, PAGE_SIZE - len, "\n");
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR(available_out_modes, S_IRUGO, tpiu_show_available_out_modes,
|
|
|
|
NULL);
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
static const struct coresight_ops tpiu_cs_ops = {
|
|
|
|
.sink_ops = &tpiu_sink_ops,
|
|
|
|
};
|
|
|
|
|
|
|
|
static ssize_t tpiu_show_set(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct tpiu_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
|
|
|
|
return scnprintf(buf, PAGE_SIZE, "%s\n",
|
|
|
|
drvdata->set == TPIU_SET_A ?
|
|
|
|
"a" : "b");
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t tpiu_store_set(struct device *dev, struct device_attribute *attr,
|
|
|
|
const char *buf, size_t size)
|
|
|
|
{
|
|
|
|
struct tpiu_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
char str[10] = "";
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (strlen(buf) >= 10)
|
|
|
|
return -EINVAL;
|
|
|
|
if (sscanf(buf, "%s", str) != 1)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mutex_lock(&drvdata->mutex);
|
|
|
|
if (!strcmp(str, "a")) {
|
|
|
|
if (drvdata->set == TPIU_SET_A)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if (!drvdata->enable || drvdata->out_mode !=
|
|
|
|
TPIU_OUT_MODE_MICTOR) {
|
|
|
|
drvdata->set = TPIU_SET_A;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
__tpiu_disable_setb(drvdata);
|
|
|
|
ret = __tpiu_enable_seta(drvdata);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(drvdata->dev, "failed to enable set A\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
drvdata->set = TPIU_SET_A;
|
|
|
|
} else if (!strcmp(str, "b")) {
|
|
|
|
if (drvdata->set == TPIU_SET_B)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if (!drvdata->enable || drvdata->out_mode !=
|
|
|
|
TPIU_OUT_MODE_MICTOR) {
|
|
|
|
drvdata->set = TPIU_SET_B;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
__tpiu_disable_seta(drvdata);
|
|
|
|
ret = __tpiu_enable_setb(drvdata);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(drvdata->dev, "failed to enable set B\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
drvdata->set = TPIU_SET_B;
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
mutex_unlock(&drvdata->mutex);
|
|
|
|
return size;
|
|
|
|
err:
|
|
|
|
mutex_unlock(&drvdata->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR(set, S_IRUGO | S_IWUSR, tpiu_show_set, tpiu_store_set);
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
static DEVICE_ATTR(nidnt_timeout_value,
|
|
|
|
S_IRUGO | S_IWUSR,
|
|
|
|
coresight_nidnt_show_timeout_value,
|
|
|
|
coresight_nidnt_store_timeout_value);
|
|
|
|
|
|
|
|
static DEVICE_ATTR(nidnt_debounce_value,
|
|
|
|
S_IRUGO | S_IWUSR,
|
|
|
|
coresight_nidnt_show_debounce_value,
|
|
|
|
coresight_nidnt_store_debounce_value);
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
static struct attribute *tpiu_attrs[] = {
|
|
|
|
&dev_attr_out_mode.attr,
|
2024-09-09 08:57:42 +00:00
|
|
|
&dev_attr_available_out_modes.attr,
|
2024-09-09 08:52:07 +00:00
|
|
|
&dev_attr_set.attr,
|
2024-09-09 08:57:42 +00:00
|
|
|
&dev_attr_nidnt_timeout_value.attr,
|
|
|
|
&dev_attr_nidnt_debounce_value.attr,
|
2024-09-09 08:52:07 +00:00
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct attribute_group tpiu_attr_grp = {
|
|
|
|
.attrs = tpiu_attrs,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct attribute_group *tpiu_attr_grps[] = {
|
|
|
|
&tpiu_attr_grp,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
static int tpiu_parse_of_data(struct platform_device *pdev,
|
2024-09-09 08:52:07 +00:00
|
|
|
struct tpiu_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
struct device_node *node = pdev->dev.of_node;
|
|
|
|
struct device_node *reg_node = NULL;
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
const __be32 *prop;
|
2024-09-09 08:57:42 +00:00
|
|
|
int len, ret;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
reg_node = of_parse_phandle(node, "vdd-supply", 0);
|
|
|
|
if (reg_node) {
|
|
|
|
drvdata->reg = devm_regulator_get(dev, "vdd");
|
|
|
|
if (IS_ERR(drvdata->reg))
|
|
|
|
return PTR_ERR(drvdata->reg);
|
|
|
|
|
|
|
|
prop = of_get_property(node, "qcom,vdd-voltage-level", &len);
|
|
|
|
if (!prop || (len != (2 * sizeof(__be32)))) {
|
|
|
|
dev_err(dev, "sdc voltage levels not specified\n");
|
|
|
|
} else {
|
|
|
|
drvdata->reg_low = be32_to_cpup(&prop[0]);
|
|
|
|
drvdata->reg_high = be32_to_cpup(&prop[1]);
|
|
|
|
}
|
|
|
|
|
|
|
|
prop = of_get_property(node, "qcom,vdd-current-level", &len);
|
|
|
|
if (!prop || (len != (2 * sizeof(__be32)))) {
|
|
|
|
dev_err(dev, "sdc current levels not specified\n");
|
|
|
|
} else {
|
|
|
|
drvdata->reg_lpm = be32_to_cpup(&prop[0]);
|
|
|
|
drvdata->reg_hpm = be32_to_cpup(&prop[1]);
|
|
|
|
}
|
|
|
|
of_node_put(reg_node);
|
|
|
|
} else {
|
|
|
|
dev_err(dev, "sdc voltage supply not specified or available\n");
|
|
|
|
}
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
reg_node = of_parse_phandle(node, "vdd-io-supply", 0);
|
|
|
|
if (reg_node) {
|
|
|
|
drvdata->reg_io = devm_regulator_get(dev, "vdd-io");
|
|
|
|
if (IS_ERR(drvdata->reg_io))
|
|
|
|
return PTR_ERR(drvdata->reg_io);
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
prop = of_get_property(node, "qcom,vdd-io-voltage-level", &len);
|
|
|
|
if (!prop || (len != (2 * sizeof(__be32)))) {
|
|
|
|
dev_err(dev, "sdc io voltage levels not specified\n");
|
|
|
|
} else {
|
|
|
|
drvdata->reg_low_io = be32_to_cpup(&prop[0]);
|
|
|
|
drvdata->reg_high_io = be32_to_cpup(&prop[1]);
|
2024-09-09 08:52:07 +00:00
|
|
|
}
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
prop = of_get_property(node, "qcom,vdd-io-current-level", &len);
|
|
|
|
if (!prop || (len != (2 * sizeof(__be32)))) {
|
|
|
|
dev_err(dev, "sdc io current levels not specified\n");
|
|
|
|
} else {
|
|
|
|
drvdata->reg_lpm_io = be32_to_cpup(&prop[0]);
|
|
|
|
drvdata->reg_hpm_io = be32_to_cpup(&prop[1]);
|
|
|
|
}
|
|
|
|
of_node_put(reg_node);
|
2024-09-09 08:52:07 +00:00
|
|
|
} else {
|
2024-09-09 08:57:42 +00:00
|
|
|
dev_err(dev,
|
|
|
|
"sdc io voltage supply not specified or available\n");
|
2024-09-09 08:52:07 +00:00
|
|
|
}
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
drvdata->out_mode = TPIU_OUT_MODE_MICTOR;
|
|
|
|
drvdata->set = TPIU_SET_B;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
drvdata->nidntsw = of_property_read_bool(pdev->dev.of_node,
|
|
|
|
"qcom,nidntsw");
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
drvdata->nidnthw = of_property_read_bool(pdev->dev.of_node,
|
|
|
|
"qcom,nidnthw");
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
if (!drvdata->nidntsw && !drvdata->nidnthw) {
|
|
|
|
dev_err(drvdata->dev,
|
|
|
|
"NIDnT hw or sw support not specified\n");
|
|
|
|
} else {
|
|
|
|
drvdata->nidnt_swduart = of_property_read_bool(
|
|
|
|
pdev->dev.of_node,
|
|
|
|
"qcom,nidnt-swduart");
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
drvdata->nidnt_swdtrc = of_property_read_bool(
|
|
|
|
pdev->dev.of_node,
|
|
|
|
"qcom,nidnt-swdtrc");
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
drvdata->nidnt_jtag = of_property_read_bool(pdev->dev.of_node,
|
|
|
|
"qcom,nidnt-jtag");
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
drvdata->nidnt_spmi = of_property_read_bool(pdev->dev.of_node,
|
|
|
|
"qcom,nidnt-spmi");
|
|
|
|
}
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
ret = coresight_nidnt_init(pdev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
if (drvdata->nidnthw) {
|
|
|
|
if (nidnt_boot_hw_detect) {
|
|
|
|
ret = __tpiu_enable_to_sdc(drvdata);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
/* enable and configure nidnt hardware detect */
|
|
|
|
coresight_nidnt_set_hwdetect_param(true);
|
|
|
|
coresight_nidnt_enable_hwdetect();
|
|
|
|
dev_info(dev, "NIDnT run-time PS enabled\n");
|
|
|
|
} else {
|
|
|
|
/* if hardware detect is disabled, disable QDSD */
|
|
|
|
ret = coresight_nidnt_config_qdsd_enable(false);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(drvdata->dev, "failed to disable QDSD\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
dev_info(dev, "NIDnT on SDCARD only mode\n");
|
|
|
|
}
|
2024-09-09 08:52:07 +00:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
static int tpiu_probe(struct platform_device *pdev)
|
2024-09-09 08:52:07 +00:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct coresight_platform_data *pdata;
|
|
|
|
struct tpiu_drvdata *drvdata;
|
|
|
|
struct resource *res;
|
|
|
|
struct coresight_desc *desc;
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
pdata = of_get_coresight_platform_data(dev, pdev->dev.of_node);
|
|
|
|
if (IS_ERR(pdata))
|
|
|
|
return PTR_ERR(pdata);
|
|
|
|
pdev->dev.platform_data = pdata;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
|
|
|
|
if (!drvdata)
|
|
|
|
return -ENOMEM;
|
|
|
|
drvdata->dev = &pdev->dev;
|
|
|
|
platform_set_drvdata(pdev, drvdata);
|
|
|
|
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tpiu-base");
|
|
|
|
if (!res)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
drvdata->base = devm_ioremap(dev, res->start, resource_size(res));
|
|
|
|
if (!drvdata->base)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
mutex_init(&drvdata->mutex);
|
|
|
|
|
|
|
|
drvdata->clk = devm_clk_get(dev, "core_clk");
|
|
|
|
if (IS_ERR(drvdata->clk))
|
|
|
|
return PTR_ERR(drvdata->clk);
|
|
|
|
|
|
|
|
ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(drvdata->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
if (!coresight_authstatus_enabled(drvdata->base)) {
|
|
|
|
clk_disable_unprepare(drvdata->clk);
|
|
|
|
return -EPERM;
|
|
|
|
}
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
/* Disable tpiu to support older targets that need this */
|
|
|
|
__tpiu_disable(drvdata);
|
|
|
|
|
|
|
|
clk_disable_unprepare(drvdata->clk);
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
ret = tpiu_parse_of_data(pdev, drvdata);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
|
|
|
if (!desc)
|
|
|
|
return -ENOMEM;
|
|
|
|
desc->type = CORESIGHT_DEV_TYPE_SINK;
|
|
|
|
desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PORT;
|
|
|
|
desc->ops = &tpiu_cs_ops;
|
|
|
|
desc->pdata = pdev->dev.platform_data;
|
|
|
|
desc->dev = &pdev->dev;
|
|
|
|
desc->groups = tpiu_attr_grps;
|
|
|
|
desc->owner = THIS_MODULE;
|
|
|
|
drvdata->csdev = coresight_register(desc);
|
|
|
|
if (IS_ERR(drvdata->csdev))
|
|
|
|
return PTR_ERR(drvdata->csdev);
|
|
|
|
|
|
|
|
dev_info(dev, "TPIU initialized\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
static int tpiu_remove(struct platform_device *pdev)
|
2024-09-09 08:52:07 +00:00
|
|
|
{
|
|
|
|
struct tpiu_drvdata *drvdata = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
coresight_unregister(drvdata->csdev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct of_device_id tpiu_match[] = {
|
|
|
|
{.compatible = "arm,coresight-tpiu"},
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_driver tpiu_driver = {
|
|
|
|
.probe = tpiu_probe,
|
2024-09-09 08:57:42 +00:00
|
|
|
.remove = tpiu_remove,
|
2024-09-09 08:52:07 +00:00
|
|
|
.driver = {
|
|
|
|
.name = "coresight-tpiu",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.of_match_table = tpiu_match,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init tpiu_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&tpiu_driver);
|
|
|
|
}
|
|
|
|
module_init(tpiu_init);
|
|
|
|
|
|
|
|
static void __exit tpiu_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&tpiu_driver);
|
|
|
|
}
|
|
|
|
module_exit(tpiu_exit);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_DESCRIPTION("CoreSight Trace Port Interface Unit driver");
|