2024-09-09 08:52:07 +00:00
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/*
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* This file contains assembly-language implementations
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* of IP-style 1's complement checksum routines.
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*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Severely hacked about by Paul Mackerras (paulus@cs.anu.edu.au).
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*/
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#include <linux/sys.h>
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#include <asm/processor.h>
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#include <asm/errno.h>
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#include <asm/ppc_asm.h>
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/*
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* ip_fast_csum(r3=buf, r4=len) -- Optimized for IP header
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* len is in words and is always >= 5.
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*
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* In practice len == 5, but this is not guaranteed. So this code does not
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* attempt to use doubleword instructions.
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*/
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_GLOBAL(ip_fast_csum)
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lwz r0,0(r3)
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lwzu r5,4(r3)
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addic. r4,r4,-2
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addc r0,r0,r5
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mtctr r4
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blelr-
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1: lwzu r4,4(r3)
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adde r0,r0,r4
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bdnz 1b
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addze r0,r0 /* add in final carry */
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rldicl r4,r0,32,0 /* fold two 32-bit halves together */
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add r0,r0,r4
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srdi r0,r0,32
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rlwinm r3,r0,16,0,31 /* fold two halves together */
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add r3,r0,r3
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not r3,r3
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srwi r3,r3,16
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blr
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/*
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* Compute checksum of TCP or UDP pseudo-header:
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* csum_tcpudp_magic(r3=saddr, r4=daddr, r5=len, r6=proto, r7=sum)
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* No real gain trying to do this specially for 64 bit, but
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* the 32 bit addition may spill into the upper bits of
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* the doubleword so we still must fold it down from 64.
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*/
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_GLOBAL(csum_tcpudp_magic)
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rlwimi r5,r6,16,0,15 /* put proto in upper half of len */
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addc r0,r3,r4 /* add 4 32-bit words together */
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adde r0,r0,r5
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adde r0,r0,r7
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rldicl r4,r0,32,0 /* fold 64 bit value */
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add r0,r4,r0
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srdi r0,r0,32
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rlwinm r3,r0,16,0,31 /* fold two halves together */
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add r3,r0,r3
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not r3,r3
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srwi r3,r3,16
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blr
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/*
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* Computes the checksum of a memory block at buff, length len,
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* and adds in "sum" (32-bit).
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*
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* csum_partial(r3=buff, r4=len, r5=sum)
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*/
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_GLOBAL(csum_partial)
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addic r0,r5,0 /* clear carry */
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srdi. r6,r4,3 /* less than 8 bytes? */
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beq .Lcsum_tail_word
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/*
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* If only halfword aligned, align to a double word. Since odd
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* aligned addresses should be rare and they would require more
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* work to calculate the correct checksum, we ignore that case
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* and take the potential slowdown of unaligned loads.
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*/
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rldicl. r6,r3,64-1,64-2 /* r6 = (r3 & 0x3) >> 1 */
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beq .Lcsum_aligned
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li r7,4
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sub r6,r7,r6
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mtctr r6
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1:
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lhz r6,0(r3) /* align to doubleword */
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subi r4,r4,2
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addi r3,r3,2
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adde r0,r0,r6
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bdnz 1b
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.Lcsum_aligned:
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/*
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* We unroll the loop such that each iteration is 64 bytes with an
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* entry and exit limb of 64 bytes, meaning a minimum size of
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* 128 bytes.
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*/
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srdi. r6,r4,7
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beq .Lcsum_tail_doublewords /* len < 128 */
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srdi r6,r4,6
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subi r6,r6,1
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mtctr r6
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stdu r1,-STACKFRAMESIZE(r1)
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2024-09-09 08:57:42 +00:00
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std r14,STK_REG(R14)(r1)
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std r15,STK_REG(R15)(r1)
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std r16,STK_REG(R16)(r1)
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2024-09-09 08:52:07 +00:00
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ld r6,0(r3)
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ld r9,8(r3)
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ld r10,16(r3)
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ld r11,24(r3)
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/*
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* On POWER6 and POWER7 back to back addes take 2 cycles because of
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* the XER dependency. This means the fastest this loop can go is
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* 16 cycles per iteration. The scheduling of the loop below has
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* been shown to hit this on both POWER6 and POWER7.
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*/
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.align 5
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2:
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adde r0,r0,r6
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ld r12,32(r3)
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ld r14,40(r3)
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adde r0,r0,r9
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ld r15,48(r3)
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ld r16,56(r3)
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addi r3,r3,64
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adde r0,r0,r10
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adde r0,r0,r11
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adde r0,r0,r12
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adde r0,r0,r14
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adde r0,r0,r15
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ld r6,0(r3)
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ld r9,8(r3)
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adde r0,r0,r16
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ld r10,16(r3)
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ld r11,24(r3)
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bdnz 2b
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adde r0,r0,r6
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ld r12,32(r3)
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ld r14,40(r3)
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adde r0,r0,r9
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ld r15,48(r3)
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ld r16,56(r3)
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addi r3,r3,64
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adde r0,r0,r10
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adde r0,r0,r11
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adde r0,r0,r12
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adde r0,r0,r14
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adde r0,r0,r15
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adde r0,r0,r16
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2024-09-09 08:57:42 +00:00
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ld r14,STK_REG(R14)(r1)
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ld r15,STK_REG(R15)(r1)
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ld r16,STK_REG(R16)(r1)
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2024-09-09 08:52:07 +00:00
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addi r1,r1,STACKFRAMESIZE
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andi. r4,r4,63
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.Lcsum_tail_doublewords: /* Up to 127 bytes to go */
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srdi. r6,r4,3
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beq .Lcsum_tail_word
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mtctr r6
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3:
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ld r6,0(r3)
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addi r3,r3,8
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adde r0,r0,r6
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bdnz 3b
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andi. r4,r4,7
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.Lcsum_tail_word: /* Up to 7 bytes to go */
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srdi. r6,r4,2
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beq .Lcsum_tail_halfword
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lwz r6,0(r3)
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addi r3,r3,4
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adde r0,r0,r6
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subi r4,r4,4
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.Lcsum_tail_halfword: /* Up to 3 bytes to go */
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srdi. r6,r4,1
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beq .Lcsum_tail_byte
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lhz r6,0(r3)
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addi r3,r3,2
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adde r0,r0,r6
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subi r4,r4,2
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.Lcsum_tail_byte: /* Up to 1 byte to go */
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andi. r6,r4,1
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beq .Lcsum_finish
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lbz r6,0(r3)
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sldi r9,r6,8 /* Pad the byte out to 16 bits */
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adde r0,r0,r9
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.Lcsum_finish:
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addze r0,r0 /* add in final carry */
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rldicl r4,r0,32,0 /* fold two 32 bit halves together */
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add r3,r4,r0
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srdi r3,r3,32
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blr
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2024-09-09 08:57:42 +00:00
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.macro srcnr
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2024-09-09 08:52:07 +00:00
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100:
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.section __ex_table,"a"
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.align 3
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2024-09-09 08:57:42 +00:00
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.llong 100b,.Lsrc_error_nr
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2024-09-09 08:52:07 +00:00
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.previous
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.endm
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2024-09-09 08:57:42 +00:00
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.macro source
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150:
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.section __ex_table,"a"
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.align 3
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.llong 150b,.Lsrc_error
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.previous
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.endm
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.macro dstnr
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2024-09-09 08:52:07 +00:00
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200:
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.section __ex_table,"a"
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.align 3
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2024-09-09 08:57:42 +00:00
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.llong 200b,.Ldest_error_nr
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.previous
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.endm
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.macro dest
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250:
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.section __ex_table,"a"
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.align 3
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.llong 250b,.Ldest_error
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2024-09-09 08:52:07 +00:00
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.previous
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.endm
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/*
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* Computes the checksum of a memory block at src, length len,
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* and adds in "sum" (32-bit), while copying the block to dst.
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* If an access exception occurs on src or dst, it stores -EFAULT
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* to *src_err or *dst_err respectively. The caller must take any action
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* required in this case (zeroing memory, recalculating partial checksum etc).
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*
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* csum_partial_copy_generic(r3=src, r4=dst, r5=len, r6=sum, r7=src_err, r8=dst_err)
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*/
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_GLOBAL(csum_partial_copy_generic)
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addic r0,r6,0 /* clear carry */
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srdi. r6,r5,3 /* less than 8 bytes? */
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beq .Lcopy_tail_word
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/*
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* If only halfword aligned, align to a double word. Since odd
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* aligned addresses should be rare and they would require more
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* work to calculate the correct checksum, we ignore that case
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* and take the potential slowdown of unaligned loads.
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*
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* If the source and destination are relatively unaligned we only
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* align the source. This keeps things simple.
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*/
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rldicl. r6,r3,64-1,64-2 /* r6 = (r3 & 0x3) >> 1 */
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beq .Lcopy_aligned
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2024-09-09 08:57:42 +00:00
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li r9,4
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sub r6,r9,r6
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2024-09-09 08:52:07 +00:00
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mtctr r6
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1:
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2024-09-09 08:57:42 +00:00
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srcnr; lhz r6,0(r3) /* align to doubleword */
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2024-09-09 08:52:07 +00:00
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subi r5,r5,2
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addi r3,r3,2
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adde r0,r0,r6
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2024-09-09 08:57:42 +00:00
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dstnr; sth r6,0(r4)
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2024-09-09 08:52:07 +00:00
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addi r4,r4,2
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bdnz 1b
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.Lcopy_aligned:
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/*
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* We unroll the loop such that each iteration is 64 bytes with an
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* entry and exit limb of 64 bytes, meaning a minimum size of
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* 128 bytes.
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*/
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srdi. r6,r5,7
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beq .Lcopy_tail_doublewords /* len < 128 */
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srdi r6,r5,6
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subi r6,r6,1
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mtctr r6
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stdu r1,-STACKFRAMESIZE(r1)
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2024-09-09 08:57:42 +00:00
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std r14,STK_REG(R14)(r1)
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std r15,STK_REG(R15)(r1)
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std r16,STK_REG(R16)(r1)
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2024-09-09 08:52:07 +00:00
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|
source; ld r6,0(r3)
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|
source; ld r9,8(r3)
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|
source; ld r10,16(r3)
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source; ld r11,24(r3)
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/*
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|
* On POWER6 and POWER7 back to back addes take 2 cycles because of
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|
* the XER dependency. This means the fastest this loop can go is
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|
* 16 cycles per iteration. The scheduling of the loop below has
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* been shown to hit this on both POWER6 and POWER7.
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*/
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.align 5
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2:
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adde r0,r0,r6
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source; ld r12,32(r3)
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|
source; ld r14,40(r3)
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adde r0,r0,r9
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source; ld r15,48(r3)
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source; ld r16,56(r3)
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addi r3,r3,64
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adde r0,r0,r10
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dest; std r6,0(r4)
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dest; std r9,8(r4)
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adde r0,r0,r11
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dest; std r10,16(r4)
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dest; std r11,24(r4)
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adde r0,r0,r12
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dest; std r12,32(r4)
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dest; std r14,40(r4)
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adde r0,r0,r14
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dest; std r15,48(r4)
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dest; std r16,56(r4)
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|
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addi r4,r4,64
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|
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adde r0,r0,r15
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|
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source; ld r6,0(r3)
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source; ld r9,8(r3)
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adde r0,r0,r16
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source; ld r10,16(r3)
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source; ld r11,24(r3)
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|
|
bdnz 2b
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|
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adde r0,r0,r6
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|
|
source; ld r12,32(r3)
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|
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source; ld r14,40(r3)
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|
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adde r0,r0,r9
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|
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source; ld r15,48(r3)
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|
|
source; ld r16,56(r3)
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|
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addi r3,r3,64
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|
|
adde r0,r0,r10
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|
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dest; std r6,0(r4)
|
|
|
|
|
dest; std r9,8(r4)
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|
|
|
adde r0,r0,r11
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|
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|
dest; std r10,16(r4)
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|
|
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dest; std r11,24(r4)
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|
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|
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adde r0,r0,r12
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|
|
dest; std r12,32(r4)
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|
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dest; std r14,40(r4)
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|
|
adde r0,r0,r14
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|
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dest; std r15,48(r4)
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|
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dest; std r16,56(r4)
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|
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addi r4,r4,64
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|
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adde r0,r0,r15
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|
|
adde r0,r0,r16
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|
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|
|
2024-09-09 08:57:42 +00:00
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|
ld r14,STK_REG(R14)(r1)
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|
|
ld r15,STK_REG(R15)(r1)
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|
|
ld r16,STK_REG(R16)(r1)
|
2024-09-09 08:52:07 +00:00
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|
|
addi r1,r1,STACKFRAMESIZE
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|
|
andi. r5,r5,63
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|
|
.Lcopy_tail_doublewords: /* Up to 127 bytes to go */
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|
|
srdi. r6,r5,3
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|
|
beq .Lcopy_tail_word
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|
|
mtctr r6
|
|
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|
3:
|
2024-09-09 08:57:42 +00:00
|
|
|
srcnr; ld r6,0(r3)
|
2024-09-09 08:52:07 +00:00
|
|
|
addi r3,r3,8
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|
|
|
|
adde r0,r0,r6
|
2024-09-09 08:57:42 +00:00
|
|
|
dstnr; std r6,0(r4)
|
2024-09-09 08:52:07 +00:00
|
|
|
addi r4,r4,8
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|
|
|
bdnz 3b
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|
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|
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|
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|
|
andi. r5,r5,7
|
|
|
|
|
|
|
|
|
|
.Lcopy_tail_word: /* Up to 7 bytes to go */
|
|
|
|
|
srdi. r6,r5,2
|
|
|
|
|
beq .Lcopy_tail_halfword
|
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
srcnr; lwz r6,0(r3)
|
2024-09-09 08:52:07 +00:00
|
|
|
addi r3,r3,4
|
|
|
|
|
adde r0,r0,r6
|
2024-09-09 08:57:42 +00:00
|
|
|
dstnr; stw r6,0(r4)
|
2024-09-09 08:52:07 +00:00
|
|
|
addi r4,r4,4
|
|
|
|
|
subi r5,r5,4
|
|
|
|
|
|
|
|
|
|
.Lcopy_tail_halfword: /* Up to 3 bytes to go */
|
|
|
|
|
srdi. r6,r5,1
|
|
|
|
|
beq .Lcopy_tail_byte
|
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
srcnr; lhz r6,0(r3)
|
2024-09-09 08:52:07 +00:00
|
|
|
addi r3,r3,2
|
|
|
|
|
adde r0,r0,r6
|
2024-09-09 08:57:42 +00:00
|
|
|
dstnr; sth r6,0(r4)
|
2024-09-09 08:52:07 +00:00
|
|
|
addi r4,r4,2
|
|
|
|
|
subi r5,r5,2
|
|
|
|
|
|
|
|
|
|
.Lcopy_tail_byte: /* Up to 1 byte to go */
|
|
|
|
|
andi. r6,r5,1
|
|
|
|
|
beq .Lcopy_finish
|
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
srcnr; lbz r6,0(r3)
|
2024-09-09 08:52:07 +00:00
|
|
|
sldi r9,r6,8 /* Pad the byte out to 16 bits */
|
|
|
|
|
adde r0,r0,r9
|
2024-09-09 08:57:42 +00:00
|
|
|
dstnr; stb r6,0(r4)
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
|
.Lcopy_finish:
|
|
|
|
|
addze r0,r0 /* add in final carry */
|
|
|
|
|
rldicl r4,r0,32,0 /* fold two 32 bit halves together */
|
|
|
|
|
add r3,r4,r0
|
|
|
|
|
srdi r3,r3,32
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.Lsrc_error:
|
2024-09-09 08:57:42 +00:00
|
|
|
ld r14,STK_REG(R14)(r1)
|
|
|
|
|
ld r15,STK_REG(R15)(r1)
|
|
|
|
|
ld r16,STK_REG(R16)(r1)
|
|
|
|
|
addi r1,r1,STACKFRAMESIZE
|
|
|
|
|
.Lsrc_error_nr:
|
2024-09-09 08:52:07 +00:00
|
|
|
cmpdi 0,r7,0
|
|
|
|
|
beqlr
|
|
|
|
|
li r6,-EFAULT
|
|
|
|
|
stw r6,0(r7)
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.Ldest_error:
|
2024-09-09 08:57:42 +00:00
|
|
|
ld r14,STK_REG(R14)(r1)
|
|
|
|
|
ld r15,STK_REG(R15)(r1)
|
|
|
|
|
ld r16,STK_REG(R16)(r1)
|
|
|
|
|
addi r1,r1,STACKFRAMESIZE
|
|
|
|
|
.Ldest_error_nr:
|
2024-09-09 08:52:07 +00:00
|
|
|
cmpdi 0,r8,0
|
|
|
|
|
beqlr
|
|
|
|
|
li r6,-EFAULT
|
|
|
|
|
stw r6,0(r8)
|
|
|
|
|
blr
|
