2024-09-09 08:52:07 +00:00
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/*
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* Copied from <file:arch/powerpc/kernel/misc_32.S>
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*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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*
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* kexec bits:
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* Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
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* GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include "ppc_asm.h"
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#define SPRN_PVR 0x11F /* Processor Version Register */
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.text
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/* udelay (on non-601 processors) needs to know the period of the
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* timebase in nanoseconds. This used to be hardcoded to be 60ns
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* (period of 66MHz/4). Now a variable is used that is initialized to
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* 60 for backward compatibility, but it can be overridden as necessary
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* with code something like this:
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* extern unsigned long timebase_period_ns;
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* timebase_period_ns = 1000000000 / bd->bi_tbfreq;
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*/
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.data
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.globl timebase_period_ns
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timebase_period_ns:
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.long 60
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.text
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/*
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* Delay for a number of microseconds
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*/
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.globl udelay
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udelay:
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mfspr r4,SPRN_PVR
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srwi r4,r4,16
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cmpwi 0,r4,1 /* 601 ? */
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bne .Ludelay_not_601
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2024-09-09 08:52:07 +00:00
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00: li r0,86 /* Instructions / microsecond? */
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mtctr r0
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10: addi r0,r0,0 /* NOP */
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bdnz 10b
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subic. r3,r3,1
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bne 00b
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blr
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2024-09-09 08:57:42 +00:00
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.Ludelay_not_601:
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2024-09-09 08:52:07 +00:00
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mulli r4,r3,1000 /* nanoseconds */
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/* Change r4 to be the number of ticks using:
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* (nanoseconds + (timebase_period_ns - 1 )) / timebase_period_ns
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* timebase_period_ns defaults to 60 (16.6MHz) */
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mflr r5
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bl 0f
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0: mflr r6
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mtlr r5
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lis r5,0b@ha
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addi r5,r5,0b@l
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subf r5,r5,r6 /* In case we're relocated */
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addis r5,r5,timebase_period_ns@ha
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lwz r5,timebase_period_ns@l(r5)
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add r4,r4,r5
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addi r4,r4,-1
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divw r4,r4,r5 /* BUS ticks */
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2024-09-09 08:57:42 +00:00
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#ifdef CONFIG_8xx
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2024-09-09 08:52:07 +00:00
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1: mftbu r5
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mftb r6
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mftbu r7
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2024-09-09 08:57:42 +00:00
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#else
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1: mfspr r5, SPRN_TBRU
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mfspr r6, SPRN_TBRL
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mfspr r7, SPRN_TBRU
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#endif
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2024-09-09 08:52:07 +00:00
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cmpw 0,r5,r7
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bne 1b /* Get [synced] base time */
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addc r9,r6,r4 /* Compute end time */
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addze r8,r5
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2024-09-09 08:57:42 +00:00
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#ifdef CONFIG_8xx
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2024-09-09 08:52:07 +00:00
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2: mftbu r5
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2024-09-09 08:57:42 +00:00
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#else
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2: mfspr r5, SPRN_TBRU
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#endif
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2024-09-09 08:52:07 +00:00
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cmpw 0,r5,r8
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blt 2b
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bgt 3f
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2024-09-09 08:57:42 +00:00
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#ifdef CONFIG_8xx
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2024-09-09 08:52:07 +00:00
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mftb r6
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2024-09-09 08:57:42 +00:00
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#else
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mfspr r6, SPRN_TBRL
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#endif
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2024-09-09 08:52:07 +00:00
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cmpw 0,r6,r9
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blt 2b
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3: blr
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