221 lines
8.3 KiB
C
221 lines
8.3 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* A small micro-assembler. It is intentionally kept simple, does only
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* support a subset of instructions, and does not try to hide pipeline
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* effects like branch delay slots.
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*
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* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
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* Copyright (C) 2005, 2007 Maciej W. Rozycki
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* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/inst.h>
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#include <asm/elf.h>
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#include <asm/bugs.h>
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#define UASM_ISA _UASM_ISA_CLASSIC
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#include <asm/uasm.h>
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#define RS_MASK 0x1f
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#define RS_SH 21
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#define RT_MASK 0x1f
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#define RT_SH 16
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#define SCIMM_MASK 0xfffff
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#define SCIMM_SH 6
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/* This macro sets the non-variable bits of an instruction. */
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#define M(a, b, c, d, e, f) \
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((a) << OP_SH \
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| (b) << RS_SH \
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| (c) << RT_SH \
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| (d) << RD_SH \
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| (e) << RE_SH \
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| (f) << FUNC_SH)
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/* Define these when we are not the ISA the kernel is being compiled with. */
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#ifdef CONFIG_CPU_MICROMIPS
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#define CL_uasm_i_b(buf, off) ISAOPC(_beq)(buf, 0, 0, off)
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#define CL_uasm_i_beqz(buf, rs, off) ISAOPC(_beq)(buf, rs, 0, off)
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#define CL_uasm_i_beqzl(buf, rs, off) ISAOPC(_beql)(buf, rs, 0, off)
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#define CL_uasm_i_bnez(buf, rs, off) ISAOPC(_bne)(buf, rs, 0, off)
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#endif
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#include "uasm.c"
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static struct insn insn_table[] = {
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{ insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
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{ insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
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{ insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
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{ insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
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{ insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
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{ insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
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{ insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
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{ insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
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{ insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
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{ insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
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{ insn_divu, M(spec_op, 0, 0, 0, 0, divu_op), RS | RT },
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{ insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
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{ insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
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{ insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
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{ insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
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{ insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
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{ insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
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{ insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
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{ insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
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{ insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
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{ insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE },
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{ insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
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{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
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{ insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
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{ insn_jalr, M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD },
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{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
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{ insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
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{ insn_lb, M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
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{ insn_lh, M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
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{ insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
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{ insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_mfhi, M(spec_op, 0, 0, 0, 0, mfhi_op), RD },
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{ insn_mflo, M(spec_op, 0, 0, 0, 0, mflo_op), RD },
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{ insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
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{ insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
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{ insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
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{ insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
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{ insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
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{ insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
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{ insn_sllv, M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD },
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{ insn_slt, M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD },
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{ insn_sltiu, M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sltu, M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD },
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{ insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
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{ insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
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{ insn_srlv, M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD },
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{ insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
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{ insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sync, M(spec_op, 0, 0, 0, 0, sync_op), RE },
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{ insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
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{ insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
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{ insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
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{ insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
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{ insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
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{ insn_wait, M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM },
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{ insn_wsbh, M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD },
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{ insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
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{ insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
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{ insn_yield, M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD },
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{ insn_invalid, 0, 0 }
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};
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#undef M
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static inline u32 build_bimm(s32 arg)
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{
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WARN(arg > 0x1ffff || arg < -0x20000,
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KERN_WARNING "Micro-assembler field overflow\n");
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WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
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return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
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}
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static inline u32 build_jimm(u32 arg)
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{
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WARN(arg & ~(JIMM_MASK << 2),
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KERN_WARNING "Micro-assembler field overflow\n");
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return (arg >> 2) & JIMM_MASK;
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}
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/*
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* The order of opcode arguments is implicitly left to right,
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* starting with RS and ending with FUNC or IMM.
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*/
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static void build_insn(u32 **buf, enum opcode opc, ...)
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{
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struct insn *ip = NULL;
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unsigned int i;
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va_list ap;
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u32 op;
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for (i = 0; insn_table[i].opcode != insn_invalid; i++)
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if (insn_table[i].opcode == opc) {
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ip = &insn_table[i];
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break;
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}
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if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
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panic("Unsupported Micro-assembler instruction %d", opc);
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op = ip->match;
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va_start(ap, opc);
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if (ip->fields & RS)
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op |= build_rs(va_arg(ap, u32));
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if (ip->fields & RT)
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op |= build_rt(va_arg(ap, u32));
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if (ip->fields & RD)
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op |= build_rd(va_arg(ap, u32));
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if (ip->fields & RE)
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op |= build_re(va_arg(ap, u32));
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if (ip->fields & SIMM)
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op |= build_simm(va_arg(ap, s32));
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if (ip->fields & UIMM)
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op |= build_uimm(va_arg(ap, u32));
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if (ip->fields & BIMM)
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op |= build_bimm(va_arg(ap, s32));
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if (ip->fields & JIMM)
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op |= build_jimm(va_arg(ap, u32));
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if (ip->fields & FUNC)
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op |= build_func(va_arg(ap, u32));
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if (ip->fields & SET)
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op |= build_set(va_arg(ap, u32));
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if (ip->fields & SCIMM)
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op |= build_scimm(va_arg(ap, u32));
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va_end(ap);
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**buf = op;
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(*buf)++;
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}
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static inline void
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__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
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{
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long laddr = (long)lab->addr;
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long raddr = (long)rel->addr;
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switch (rel->type) {
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case R_MIPS_PC16:
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*rel->addr |= build_bimm(laddr - (raddr + 4));
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break;
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default:
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panic("Unsupported Micro-assembler relocation %d",
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rel->type);
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}
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}
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