2024-09-09 08:52:07 +00:00
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/*
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* Definitions for the Ethernet registers
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*
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* Copyright 2002 Allend Stichter <allen.stichter@idt.com>
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* Copyright 2008 Florian Fainelli <florian@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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2024-09-09 08:57:42 +00:00
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#ifndef __ASM_RC32434_ETH_H
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#define __ASM_RC32434_ETH_H
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2024-09-09 08:52:07 +00:00
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#define ETH0_BASE_ADDR 0x18060000
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struct eth_regs {
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u32 ethintfc;
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u32 ethfifott;
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u32 etharc;
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u32 ethhash0;
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u32 ethhash1;
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u32 ethu0[4]; /* Reserved. */
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u32 ethpfs;
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u32 ethmcp;
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u32 eth_u1[10]; /* Reserved. */
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u32 ethspare;
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u32 eth_u2[42]; /* Reserved. */
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u32 ethsal0;
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u32 ethsah0;
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u32 ethsal1;
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u32 ethsah1;
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u32 ethsal2;
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u32 ethsah2;
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u32 ethsal3;
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u32 ethsah3;
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u32 ethrbc;
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u32 ethrpc;
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u32 ethrupc;
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u32 ethrfc;
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u32 ethtbc;
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u32 ethgpf;
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u32 eth_u9[50]; /* Reserved. */
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u32 ethmac1;
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u32 ethmac2;
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u32 ethipgt;
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u32 ethipgr;
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u32 ethclrt;
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u32 ethmaxf;
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u32 eth_u10; /* Reserved. */
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u32 ethmtest;
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u32 miimcfg;
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u32 miimcmd;
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u32 miimaddr;
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u32 miimwtd;
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u32 miimrdd;
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u32 miimind;
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u32 eth_u11; /* Reserved. */
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u32 eth_u12; /* Reserved. */
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u32 ethcfsa0;
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u32 ethcfsa1;
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u32 ethcfsa2;
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};
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/* Ethernet interrupt registers */
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#define ETH_INT_FC_EN (1 << 0)
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#define ETH_INT_FC_ITS (1 << 1)
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#define ETH_INT_FC_RIP (1 << 2)
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#define ETH_INT_FC_JAM (1 << 3)
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#define ETH_INT_FC_OVR (1 << 4)
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#define ETH_INT_FC_UND (1 << 5)
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#define ETH_INT_FC_IOC 0x000000c0
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/* Ethernet FIFO registers */
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#define ETH_FIFI_TT_TTH_BIT 0
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#define ETH_FIFO_TT_TTH 0x0000007f
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/* Ethernet ARC/multicast registers */
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#define ETH_ARC_PRO (1 << 0)
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#define ETH_ARC_AM (1 << 1)
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#define ETH_ARC_AFM (1 << 2)
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#define ETH_ARC_AB (1 << 3)
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/* Ethernet SAL registers */
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#define ETH_SAL_BYTE_5 0x000000ff
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#define ETH_SAL_BYTE_4 0x0000ff00
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#define ETH_SAL_BYTE_3 0x00ff0000
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#define ETH_SAL_BYTE_2 0xff000000
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/* Ethernet SAH registers */
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#define ETH_SAH_BYTE1 0x000000ff
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#define ETH_SAH_BYTE0 0x0000ff00
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/* Ethernet GPF register */
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#define ETH_GPF_PTV 0x0000ffff
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/* Ethernet PFG register */
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#define ETH_PFS_PFD (1 << 0)
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/* Ethernet CFSA[0-3] registers */
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#define ETH_CFSA0_CFSA4 0x000000ff
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#define ETH_CFSA0_CFSA5 0x0000ff00
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#define ETH_CFSA1_CFSA2 0x000000ff
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#define ETH_CFSA1_CFSA3 0x0000ff00
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#define ETH_CFSA1_CFSA0 0x000000ff
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#define ETH_CFSA1_CFSA1 0x0000ff00
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/* Ethernet MAC1 registers */
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#define ETH_MAC1_RE (1 << 0)
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#define ETH_MAC1_PAF (1 << 1)
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#define ETH_MAC1_RFC (1 << 2)
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#define ETH_MAC1_TFC (1 << 3)
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#define ETH_MAC1_LB (1 << 4)
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#define ETH_MAC1_MR (1 << 31)
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/* Ethernet MAC2 registers */
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#define ETH_MAC2_FD (1 << 0)
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#define ETH_MAC2_FLC (1 << 1)
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#define ETH_MAC2_HFE (1 << 2)
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#define ETH_MAC2_DC (1 << 3)
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#define ETH_MAC2_CEN (1 << 4)
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#define ETH_MAC2_PE (1 << 5)
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#define ETH_MAC2_VPE (1 << 6)
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#define ETH_MAC2_APE (1 << 7)
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#define ETH_MAC2_PPE (1 << 8)
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#define ETH_MAC2_LPE (1 << 9)
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#define ETH_MAC2_NB (1 << 12)
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#define ETH_MAC2_BP (1 << 13)
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#define ETH_MAC2_ED (1 << 14)
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/* Ethernet IPGT register */
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#define ETH_IPGT 0x0000007f
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/* Ethernet IPGR registers */
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#define ETH_IPGR_IPGR2 0x0000007f
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#define ETH_IPGR_IPGR1 0x00007f00
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/* Ethernet CLRT registers */
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#define ETH_CLRT_MAX_RET 0x0000000f
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#define ETH_CLRT_COL_WIN 0x00003f00
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/* Ethernet MAXF register */
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#define ETH_MAXF 0x0000ffff
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/* Ethernet test registers */
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#define ETH_TEST_REG (1 << 2)
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#define ETH_MCP_DIV 0x000000ff
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/* MII registers */
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#define ETH_MII_CFG_RSVD 0x0000000c
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#define ETH_MII_CMD_RD (1 << 0)
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#define ETH_MII_CMD_SCN (1 << 1)
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#define ETH_MII_REG_ADDR 0x0000001f
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#define ETH_MII_PHY_ADDR 0x00001f00
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#define ETH_MII_WTD_DATA 0x0000ffff
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#define ETH_MII_RDD_DATA 0x0000ffff
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#define ETH_MII_IND_BSY (1 << 0)
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#define ETH_MII_IND_SCN (1 << 1)
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#define ETH_MII_IND_NV (1 << 2)
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/*
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* Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
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*/
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#define ETH_RX_FD (1 << 0)
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#define ETH_RX_LD (1 << 1)
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#define ETH_RX_ROK (1 << 2)
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#define ETH_RX_FM (1 << 3)
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#define ETH_RX_MP (1 << 4)
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#define ETH_RX_BP (1 << 5)
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#define ETH_RX_VLT (1 << 6)
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#define ETH_RX_CF (1 << 7)
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#define ETH_RX_OVR (1 << 8)
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#define ETH_RX_CRC (1 << 9)
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#define ETH_RX_CV (1 << 10)
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#define ETH_RX_DB (1 << 11)
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#define ETH_RX_LE (1 << 12)
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#define ETH_RX_LOR (1 << 13)
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#define ETH_RX_CES (1 << 14)
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#define ETH_RX_LEN_BIT 16
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#define ETH_RX_LEN 0xffff0000
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#define ETH_TX_FD (1 << 0)
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#define ETH_TX_LD (1 << 1)
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#define ETH_TX_OEN (1 << 2)
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#define ETH_TX_PEN (1 << 3)
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#define ETH_TX_CEN (1 << 4)
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#define ETH_TX_HEN (1 << 5)
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#define ETH_TX_TOK (1 << 6)
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#define ETH_TX_MP (1 << 7)
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#define ETH_TX_BP (1 << 8)
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#define ETH_TX_UND (1 << 9)
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#define ETH_TX_OF (1 << 10)
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#define ETH_TX_ED (1 << 11)
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#define ETH_TX_EC (1 << 12)
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#define ETH_TX_LC (1 << 13)
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#define ETH_TX_TD (1 << 14)
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#define ETH_TX_CRC (1 << 15)
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#define ETH_TX_LE (1 << 16)
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#define ETH_TX_CC 0x001E0000
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2024-09-09 08:57:42 +00:00
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#endif /* __ASM_RC32434_ETH_H */
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