2024-09-09 08:52:07 +00:00
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/*
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* irq.h: IRQ mappings for PNX833X.
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*
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* Copyright 2008 NXP Semiconductors
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* Chris Steel <chris.steel@nxp.com>
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* Daniel Laird <daniel.j.laird@nxp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
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#define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
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/*
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* The "IRQ numbers" are completely virtual.
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*
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* In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
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* Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
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* numbers 49..64 for (virtual) GPIO interrupts.
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*
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* In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
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* connected to PIC, which uses core hardware interrupt 2, and also
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* a timer interrupt through hardware interrupt 5.
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* Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
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* numbers 65..80 for (virtual) GPIO interrupts.
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*
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*/
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#include <irq.h>
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#define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7)
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/* Interrupts supported by PIC */
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2024-09-09 08:57:42 +00:00
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#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1)
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#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2)
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#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3)
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#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4)
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#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5)
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#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6)
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#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7)
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#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8)
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#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9)
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2024-09-09 08:52:07 +00:00
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#define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10)
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#define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11)
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#define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12)
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#define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13)
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#define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13)
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#define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14)
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#define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15)
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#define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16)
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#define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17)
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#define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18)
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#define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19)
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#define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20)
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#define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21)
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#define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22)
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#define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23)
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#define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24)
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#define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25)
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#define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26)
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#define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27)
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#define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28)
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#define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29)
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#define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30)
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#define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31)
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#define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32)
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#define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33)
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#define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34)
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#define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35)
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#define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36)
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#if defined(CONFIG_SOC_PNX8335)
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#define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37)
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#define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38)
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#define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39)
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#define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40)
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#define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41)
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#define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42)
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#define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43)
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#define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44)
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#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45)
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#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46)
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#define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47)
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#define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48)
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#define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49)
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#define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50)
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#define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51)
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#define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52)
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#define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53)
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#define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54)
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#define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55)
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#define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56)
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#define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57)
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#endif
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/* GPIO interrupts */
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#define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0)
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#define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1)
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#define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2)
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#define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3)
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#define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4)
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#define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5)
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#define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6)
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#define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7)
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#define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8)
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#define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9)
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#define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10)
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#define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11)
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#define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12)
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#define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13)
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#define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14)
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#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15)
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#endif
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