2024-09-09 08:52:07 +00:00
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/*
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* gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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* Copyright (C) 2005 John DeHority
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* Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
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*
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* Licensed under the GPL-2.
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*/
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#ifndef _BLACKFIN_TIMERS_H_
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#define _BLACKFIN_TIMERS_H_
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#include <linux/types.h>
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#include <asm/blackfin.h>
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/*
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* BF51x/BF52x/BF537: 8 timers:
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*/
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#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || defined(BF537_FAMILY)
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# define MAX_BLACKFIN_GPTIMERS 8
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# define TIMER0_GROUP_REG TIMER_ENABLE
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#endif
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/*
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* BF54x: 11 timers (BF542: 8 timers):
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*/
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#if defined(CONFIG_BF54x)
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# ifdef CONFIG_BF542
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# define MAX_BLACKFIN_GPTIMERS 8
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# else
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# define MAX_BLACKFIN_GPTIMERS 11
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# define TIMER8_GROUP_REG TIMER_ENABLE1
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# define TIMER_GROUP2 1
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# endif
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# define TIMER0_GROUP_REG TIMER_ENABLE0
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#endif
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/*
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* BF561: 12 timers:
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*/
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#if defined(CONFIG_BF561)
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# define MAX_BLACKFIN_GPTIMERS 12
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# define TIMER0_GROUP_REG TMRS8_ENABLE
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# define TIMER8_GROUP_REG TMRS4_ENABLE
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# define TIMER_GROUP2 1
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#endif
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2024-09-09 08:57:42 +00:00
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/*
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* BF609: 8 timers:
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*/
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#if defined(CONFIG_BF60x)
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# define MAX_BLACKFIN_GPTIMERS 8
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# define TIMER0_GROUP_REG TIMER_RUN
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#endif
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2024-09-09 08:52:07 +00:00
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/*
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* All others: 3 timers:
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*/
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#define TIMER_GROUP1 0
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#if !defined(MAX_BLACKFIN_GPTIMERS)
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# define MAX_BLACKFIN_GPTIMERS 3
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# define TIMER0_GROUP_REG TIMER_ENABLE
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#endif
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#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1)
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#define BFIN_TIMER_OCTET(x) ((x) >> 3)
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/* used in masks for timer_enable() and timer_disable() */
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#define TIMER0bit 0x0001 /* 0001b */
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#define TIMER1bit 0x0002 /* 0010b */
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#define TIMER2bit 0x0004 /* 0100b */
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#define TIMER3bit 0x0008
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#define TIMER4bit 0x0010
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#define TIMER5bit 0x0020
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#define TIMER6bit 0x0040
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#define TIMER7bit 0x0080
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#define TIMER8bit 0x0100
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#define TIMER9bit 0x0200
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#define TIMER10bit 0x0400
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#define TIMER11bit 0x0800
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#define TIMER0_id 0
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#define TIMER1_id 1
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#define TIMER2_id 2
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#define TIMER3_id 3
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#define TIMER4_id 4
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#define TIMER5_id 5
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#define TIMER6_id 6
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#define TIMER7_id 7
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#define TIMER8_id 8
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#define TIMER9_id 9
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#define TIMER10_id 10
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#define TIMER11_id 11
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/* associated timers for ppi framesync: */
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#if defined(CONFIG_BF561)
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# define FS0_1_TIMER_ID TIMER8_id
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# define FS0_2_TIMER_ID TIMER9_id
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# define FS1_1_TIMER_ID TIMER10_id
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# define FS1_2_TIMER_ID TIMER11_id
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# define FS0_1_TIMER_BIT TIMER8bit
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# define FS0_2_TIMER_BIT TIMER9bit
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# define FS1_1_TIMER_BIT TIMER10bit
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# define FS1_2_TIMER_BIT TIMER11bit
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# undef FS1_TIMER_ID
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# undef FS2_TIMER_ID
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# undef FS1_TIMER_BIT
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# undef FS2_TIMER_BIT
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#else
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# define FS1_TIMER_ID TIMER0_id
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# define FS2_TIMER_ID TIMER1_id
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# define FS1_TIMER_BIT TIMER0bit
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# define FS2_TIMER_BIT TIMER1bit
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#endif
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2024-09-09 08:57:42 +00:00
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#ifdef CONFIG_BF60x
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/*
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* Timer Configuration Register Bits
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*/
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#define TIMER_EMU_RUN 0x8000
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#define TIMER_BPER_EN 0x4000
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#define TIMER_BWID_EN 0x2000
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#define TIMER_BDLY_EN 0x1000
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#define TIMER_OUT_DIS 0x0800
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#define TIMER_TIN_SEL 0x0400
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#define TIMER_CLK_SEL 0x0300
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#define TIMER_CLK_SCLK 0x0000
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#define TIMER_CLK_ALT_CLK0 0x0100
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#define TIMER_CLK_ALT_CLK1 0x0300
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#define TIMER_PULSE_HI 0x0080
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#define TIMER_SLAVE_TRIG 0x0040
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#define TIMER_IRQ_MODE 0x0030
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#define TIMER_IRQ_ACT_EDGE 0x0000
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#define TIMER_IRQ_DLY 0x0010
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#define TIMER_IRQ_WID_DLY 0x0020
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#define TIMER_IRQ_PER 0x0030
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#define TIMER_MODE 0x000f
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#define TIMER_MODE_WDOG_P 0x0008
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#define TIMER_MODE_WDOG_W 0x0009
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#define TIMER_MODE_PWM_CONT 0x000c
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#define TIMER_MODE_PWM 0x000d
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#define TIMER_MODE_WDTH 0x000a
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#define TIMER_MODE_WDTH_D 0x000b
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#define TIMER_MODE_EXT_CLK 0x000e
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#define TIMER_MODE_PININT 0x000f
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/*
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* Timer Status Register Bits
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*/
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#define TIMER_STATUS_TIMIL0 0x0001
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#define TIMER_STATUS_TIMIL1 0x0002
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#define TIMER_STATUS_TIMIL2 0x0004
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#define TIMER_STATUS_TIMIL3 0x0008
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#define TIMER_STATUS_TIMIL4 0x0010
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#define TIMER_STATUS_TIMIL5 0x0020
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#define TIMER_STATUS_TIMIL6 0x0040
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#define TIMER_STATUS_TIMIL7 0x0080
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#define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */
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#define TIMER_STATUS_TOVF1 0x0002
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#define TIMER_STATUS_TOVF2 0x0004
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#define TIMER_STATUS_TOVF3 0x0008
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#define TIMER_STATUS_TOVF4 0x0010
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#define TIMER_STATUS_TOVF5 0x0020
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#define TIMER_STATUS_TOVF6 0x0040
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#define TIMER_STATUS_TOVF7 0x0080
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/*
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* Timer Slave Enable Status : write 1 to clear
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*/
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#define TIMER_STATUS_TRUN0 0x0001
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#define TIMER_STATUS_TRUN1 0x0002
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#define TIMER_STATUS_TRUN2 0x0004
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#define TIMER_STATUS_TRUN3 0x0008
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#define TIMER_STATUS_TRUN4 0x0010
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#define TIMER_STATUS_TRUN5 0x0020
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#define TIMER_STATUS_TRUN6 0x0040
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#define TIMER_STATUS_TRUN7 0x0080
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#else
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2024-09-09 08:52:07 +00:00
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/*
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* Timer Configuration Register Bits
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*/
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#define TIMER_ERR 0xC000
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#define TIMER_ERR_OVFL 0x4000
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#define TIMER_ERR_PROG_PER 0x8000
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#define TIMER_ERR_PROG_PW 0xC000
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#define TIMER_EMU_RUN 0x0200
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#define TIMER_TOGGLE_HI 0x0100
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#define TIMER_CLK_SEL 0x0080
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#define TIMER_OUT_DIS 0x0040
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#define TIMER_TIN_SEL 0x0020
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#define TIMER_IRQ_ENA 0x0010
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#define TIMER_PERIOD_CNT 0x0008
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#define TIMER_PULSE_HI 0x0004
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#define TIMER_MODE 0x0003
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#define TIMER_MODE_PWM 0x0001
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#define TIMER_MODE_WDTH 0x0002
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#define TIMER_MODE_EXT_CLK 0x0003
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/*
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* Timer Status Register Bits
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*/
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#define TIMER_STATUS_TIMIL0 0x0001
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#define TIMER_STATUS_TIMIL1 0x0002
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#define TIMER_STATUS_TIMIL2 0x0004
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#define TIMER_STATUS_TIMIL3 0x00000008
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#define TIMER_STATUS_TIMIL4 0x00010000
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#define TIMER_STATUS_TIMIL5 0x00020000
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#define TIMER_STATUS_TIMIL6 0x00040000
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#define TIMER_STATUS_TIMIL7 0x00080000
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#define TIMER_STATUS_TIMIL8 0x0001
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#define TIMER_STATUS_TIMIL9 0x0002
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#define TIMER_STATUS_TIMIL10 0x0004
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#define TIMER_STATUS_TIMIL11 0x0008
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#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */
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#define TIMER_STATUS_TOVF1 0x0020
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#define TIMER_STATUS_TOVF2 0x0040
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#define TIMER_STATUS_TOVF3 0x00000080
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#define TIMER_STATUS_TOVF4 0x00100000
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#define TIMER_STATUS_TOVF5 0x00200000
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#define TIMER_STATUS_TOVF6 0x00400000
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#define TIMER_STATUS_TOVF7 0x00800000
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#define TIMER_STATUS_TOVF8 0x0010
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#define TIMER_STATUS_TOVF9 0x0020
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#define TIMER_STATUS_TOVF10 0x0040
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#define TIMER_STATUS_TOVF11 0x0080
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/*
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* Timer Slave Enable Status : write 1 to clear
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*/
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#define TIMER_STATUS_TRUN0 0x1000
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#define TIMER_STATUS_TRUN1 0x2000
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#define TIMER_STATUS_TRUN2 0x4000
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#define TIMER_STATUS_TRUN3 0x00008000
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#define TIMER_STATUS_TRUN4 0x10000000
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#define TIMER_STATUS_TRUN5 0x20000000
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#define TIMER_STATUS_TRUN6 0x40000000
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#define TIMER_STATUS_TRUN7 0x80000000
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#define TIMER_STATUS_TRUN 0xF000F000
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#define TIMER_STATUS_TRUN8 0x1000
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#define TIMER_STATUS_TRUN9 0x2000
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#define TIMER_STATUS_TRUN10 0x4000
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#define TIMER_STATUS_TRUN11 0x8000
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2024-09-09 08:57:42 +00:00
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#endif
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2024-09-09 08:52:07 +00:00
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/* The actual gptimer API */
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void set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
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uint32_t get_gptimer_pwidth(unsigned int timer_id);
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void set_gptimer_period(unsigned int timer_id, uint32_t period);
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uint32_t get_gptimer_period(unsigned int timer_id);
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2024-09-09 08:57:42 +00:00
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#ifdef CONFIG_BF60x
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void set_gptimer_delay(unsigned int timer_id, uint32_t delay);
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uint32_t get_gptimer_delay(unsigned int timer_id);
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#endif
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2024-09-09 08:52:07 +00:00
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uint32_t get_gptimer_count(unsigned int timer_id);
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int get_gptimer_intr(unsigned int timer_id);
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void clear_gptimer_intr(unsigned int timer_id);
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int get_gptimer_over(unsigned int timer_id);
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void clear_gptimer_over(unsigned int timer_id);
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void set_gptimer_config(unsigned int timer_id, uint16_t config);
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uint16_t get_gptimer_config(unsigned int timer_id);
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int get_gptimer_run(unsigned int timer_id);
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void set_gptimer_pulse_hi(unsigned int timer_id);
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void clear_gptimer_pulse_hi(unsigned int timer_id);
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void enable_gptimers(uint16_t mask);
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void disable_gptimers(uint16_t mask);
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void disable_gptimers_sync(uint16_t mask);
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uint16_t get_enabled_gptimers(void);
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uint32_t get_gptimer_status(unsigned int group);
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void set_gptimer_status(unsigned int group, uint32_t value);
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static inline void enable_gptimer(unsigned int timer_id)
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{
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enable_gptimers(1 << timer_id);
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}
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static inline void disable_gptimer(unsigned int timer_id)
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{
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disable_gptimers(1 << timer_id);
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}
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/*
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* All Blackfin system MMRs are padded to 32bits even if the register
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* itself is only 16bits. So use a helper macro to streamline this.
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*/
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#define __BFP(m) u16 m; u16 __pad_##m
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/*
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* bfin timer registers layout
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*/
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struct bfin_gptimer_regs {
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__BFP(config);
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u32 counter;
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u32 period;
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u32 width;
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2024-09-09 08:57:42 +00:00
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#ifdef CONFIG_BF60x
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u32 delay;
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#endif
|
2024-09-09 08:52:07 +00:00
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};
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/*
|
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|
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* bfin group timer registers layout
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*/
|
2024-09-09 08:57:42 +00:00
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#ifndef CONFIG_BF60x
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2024-09-09 08:52:07 +00:00
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struct bfin_gptimer_group_regs {
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|
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__BFP(enable);
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|
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|
__BFP(disable);
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|
|
|
u32 status;
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};
|
2024-09-09 08:57:42 +00:00
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#else
|
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|
|
|
struct bfin_gptimer_group_regs {
|
|
|
|
|
__BFP(run);
|
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|
|
|
__BFP(enable);
|
|
|
|
|
__BFP(disable);
|
|
|
|
|
__BFP(stop_cfg);
|
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|
|
|
__BFP(stop_cfg_set);
|
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|
|
|
__BFP(stop_cfg_clr);
|
|
|
|
|
__BFP(data_imsk);
|
|
|
|
|
__BFP(stat_imsk);
|
|
|
|
|
__BFP(tr_msk);
|
|
|
|
|
__BFP(tr_ie);
|
|
|
|
|
__BFP(data_ilat);
|
|
|
|
|
__BFP(stat_ilat);
|
|
|
|
|
__BFP(err_status);
|
|
|
|
|
__BFP(bcast_per);
|
|
|
|
|
__BFP(bcast_wid);
|
|
|
|
|
__BFP(bcast_dly);
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
#endif
|
2024-09-09 08:52:07 +00:00
|
|
|
|
|
|
|
|
#undef __BFP
|
|
|
|
|
|
|
|
|
|
#endif
|
