379 lines
8.1 KiB
C
379 lines
8.1 KiB
C
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/*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/smp_plat.h>
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#include "scm-boot.h"
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#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x35a0
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#define SCSS_CPU1CORE_RESET 0x2d80
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#define SCSS_DBG_STATUS_CORE_PWRDUP 0x2e64
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#define APCS_CPU_PWR_CTL 0x04
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#define PLL_CLAMP BIT(8)
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#define CORE_PWRD_UP BIT(7)
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#define COREPOR_RST BIT(5)
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#define CORE_RST BIT(4)
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#define L2DT_SLP BIT(3)
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#define CLAMP BIT(0)
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#define APC_PWR_GATE_CTL 0x14
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#define BHS_CNT_SHIFT 24
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#define LDO_PWR_DWN_SHIFT 16
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#define LDO_BYP_SHIFT 8
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#define BHS_SEG_SHIFT 1
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#define BHS_EN BIT(0)
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#define APCS_SAW2_VCTL 0x14
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#define APCS_SAW2_2_VCTL 0x1c
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extern void secondary_startup(void);
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static DEFINE_SPINLOCK(boot_lock);
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#ifdef CONFIG_HOTPLUG_CPU
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static void __ref qcom_cpu_die(unsigned int cpu)
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{
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wfi();
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}
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#endif
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static void qcom_secondary_init(unsigned int cpu)
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{
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static int scss_release_secondary(unsigned int cpu)
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{
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struct device_node *node;
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void __iomem *base;
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node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660");
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if (!node) {
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pr_err("%s: can't find node\n", __func__);
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return -ENXIO;
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}
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base = of_iomap(node, 0);
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of_node_put(node);
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if (!base)
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return -ENOMEM;
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writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
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writel_relaxed(0, base + SCSS_CPU1CORE_RESET);
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writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP);
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mb();
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iounmap(base);
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return 0;
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}
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static int kpssv1_release_secondary(unsigned int cpu)
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{
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int ret = 0;
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void __iomem *reg, *saw_reg;
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struct device_node *cpu_node, *acc_node, *saw_node;
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u32 val;
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cpu_node = of_get_cpu_node(cpu, NULL);
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if (!cpu_node)
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return -ENODEV;
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acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
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if (!acc_node) {
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ret = -ENODEV;
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goto out_acc;
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}
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saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
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if (!saw_node) {
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ret = -ENODEV;
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goto out_saw;
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}
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reg = of_iomap(acc_node, 0);
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if (!reg) {
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ret = -ENOMEM;
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goto out_acc_map;
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}
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saw_reg = of_iomap(saw_node, 0);
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if (!saw_reg) {
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ret = -ENOMEM;
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goto out_saw_map;
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}
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/* Turn on CPU rail */
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writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
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mb();
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udelay(512);
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/* Krait bring-up sequence */
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val = PLL_CLAMP | L2DT_SLP | CLAMP;
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writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
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val &= ~L2DT_SLP;
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writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
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mb();
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ndelay(300);
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val |= COREPOR_RST;
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writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
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mb();
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udelay(2);
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val &= ~CLAMP;
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writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
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mb();
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udelay(2);
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val &= ~COREPOR_RST;
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writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
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mb();
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udelay(100);
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val |= CORE_PWRD_UP;
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writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
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mb();
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iounmap(saw_reg);
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out_saw_map:
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iounmap(reg);
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out_acc_map:
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of_node_put(saw_node);
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out_saw:
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of_node_put(acc_node);
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out_acc:
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of_node_put(cpu_node);
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return ret;
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}
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static int kpssv2_release_secondary(unsigned int cpu)
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{
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void __iomem *reg;
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struct device_node *cpu_node, *l2_node, *acc_node, *saw_node;
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void __iomem *l2_saw_base;
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unsigned reg_val;
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int ret;
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cpu_node = of_get_cpu_node(cpu, NULL);
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if (!cpu_node)
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return -ENODEV;
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acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
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if (!acc_node) {
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ret = -ENODEV;
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goto out_acc;
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}
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l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
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if (!l2_node) {
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ret = -ENODEV;
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goto out_l2;
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}
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saw_node = of_parse_phandle(l2_node, "qcom,saw", 0);
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if (!saw_node) {
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ret = -ENODEV;
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goto out_saw;
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}
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reg = of_iomap(acc_node, 0);
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if (!reg) {
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ret = -ENOMEM;
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goto out_map;
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}
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l2_saw_base = of_iomap(saw_node, 0);
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if (!l2_saw_base) {
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ret = -ENOMEM;
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goto out_saw_map;
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}
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/* Turn on the BHS, turn off LDO Bypass and power down LDO */
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reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN;
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writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
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mb();
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/* wait for the BHS to settle */
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udelay(1);
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/* Turn on BHS segments */
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reg_val |= 0x3f << BHS_SEG_SHIFT;
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writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
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mb();
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/* wait for the BHS to settle */
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udelay(1);
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/* Finally turn on the bypass so that BHS supplies power */
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reg_val |= 0x3f << LDO_BYP_SHIFT;
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writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
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/* enable max phases */
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writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL);
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mb();
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udelay(50);
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reg_val = COREPOR_RST | CLAMP;
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writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
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mb();
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udelay(2);
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reg_val &= ~CLAMP;
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writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
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mb();
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udelay(2);
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reg_val &= ~COREPOR_RST;
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writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
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mb();
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reg_val |= CORE_PWRD_UP;
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writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
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mb();
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ret = 0;
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iounmap(l2_saw_base);
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out_saw_map:
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iounmap(reg);
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out_map:
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of_node_put(saw_node);
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out_saw:
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of_node_put(l2_node);
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out_l2:
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of_node_put(acc_node);
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out_acc:
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of_node_put(cpu_node);
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return ret;
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}
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static DEFINE_PER_CPU(int, cold_boot_done);
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static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
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{
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int ret = 0;
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if (!per_cpu(cold_boot_done, cpu)) {
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ret = func(cpu);
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if (!ret)
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per_cpu(cold_boot_done, cpu) = true;
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}
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return ret;
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}
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static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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return qcom_boot_secondary(cpu, scss_release_secondary);
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}
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static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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return qcom_boot_secondary(cpu, kpssv1_release_secondary);
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}
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static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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return qcom_boot_secondary(cpu, kpssv2_release_secondary);
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}
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static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
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{
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int cpu, map;
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unsigned int flags = 0;
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static const int cold_boot_flags[] = {
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0,
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SCM_FLAG_COLDBOOT_CPU1,
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SCM_FLAG_COLDBOOT_CPU2,
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SCM_FLAG_COLDBOOT_CPU3,
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};
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for_each_present_cpu(cpu) {
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map = cpu_logical_map(cpu);
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if (WARN_ON(map >= ARRAY_SIZE(cold_boot_flags))) {
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set_cpu_present(cpu, false);
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continue;
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}
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flags |= cold_boot_flags[map];
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}
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if (scm_set_boot_addr(virt_to_phys(secondary_startup), flags)) {
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for_each_present_cpu(cpu) {
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if (cpu == smp_processor_id())
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continue;
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set_cpu_present(cpu, false);
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}
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pr_warn("Failed to set CPU boot address, disabling SMP\n");
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}
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}
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static struct smp_operations smp_msm8660_ops __initdata = {
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.smp_prepare_cpus = qcom_smp_prepare_cpus,
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.smp_secondary_init = qcom_secondary_init,
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.smp_boot_secondary = msm8660_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = qcom_cpu_die,
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#endif
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};
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CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
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static struct smp_operations qcom_smp_kpssv1_ops __initdata = {
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.smp_prepare_cpus = qcom_smp_prepare_cpus,
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.smp_secondary_init = qcom_secondary_init,
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.smp_boot_secondary = kpssv1_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = qcom_cpu_die,
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#endif
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};
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CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops);
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static struct smp_operations qcom_smp_kpssv2_ops __initdata = {
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.smp_prepare_cpus = qcom_smp_prepare_cpus,
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.smp_secondary_init = qcom_secondary_init,
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.smp_boot_secondary = kpssv2_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = qcom_cpu_die,
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#endif
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};
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CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops);
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