2024-09-09 08:52:07 +00:00
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#ifndef __ASM_MACH_ADDR_MAP_H
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#define __ASM_MACH_ADDR_MAP_H
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/*
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* Chip Selects
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*/
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#define PXA_CS0_PHYS 0x00000000
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#define PXA_CS1_PHYS 0x04000000
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#define PXA_CS2_PHYS 0x08000000
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#define PXA_CS3_PHYS 0x0C000000
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#define PXA_CS4_PHYS 0x10000000
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#define PXA_CS5_PHYS 0x14000000
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#define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
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#define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
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#define PXA3xx_CS2_PHYS 0x10000000
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#define PXA3xx_CS3_PHYS 0x14000000
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/*
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* Peripheral Bus
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*/
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#define PERIPH_PHYS 0x40000000
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#define PERIPH_VIRT IOMEM(0xf2000000)
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#define PERIPH_SIZE 0x02000000
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/*
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* Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x)
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*/
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#define PXA2XX_SMEMC_PHYS 0x48000000
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#define PXA3XX_SMEMC_PHYS 0x4a000000
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#define SMEMC_VIRT IOMEM(0xf6000000)
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#define SMEMC_SIZE 0x00100000
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/*
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* Dynamic Memory Controller (only on PXA3xx)
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*/
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#define DMEMC_PHYS 0x48100000
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#define DMEMC_VIRT IOMEM(0xf6100000)
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#define DMEMC_SIZE 0x00100000
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2024-09-09 08:57:42 +00:00
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/*
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* Reserved space for low level debug virtual addresses within
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* 0xf6200000..0xf6201000
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*/
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2024-09-09 08:52:07 +00:00
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/*
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* Internal Memory Controller (PXA27x and later)
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*/
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#define IMEMC_PHYS 0x58000000
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#define IMEMC_VIRT IOMEM(0xfe000000)
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#define IMEMC_SIZE 0x00100000
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#endif /* __ASM_MACH_ADDR_MAP_H */
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