2024-09-09 08:52:07 +00:00
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/*
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* arch/arm/include/asm/hardware/iop3xx.h
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*
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* Intel IOP32X and IOP33X register definitions
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*
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* Author: Rory Bolt <rorybolt@pacbell.net>
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* Copyright (C) 2002 Rory Bolt
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* Copyright (C) 2004 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __IOP3XX_H
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#define __IOP3XX_H
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/*
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* IOP3XX GPIO handling
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*/
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#define IOP3XX_GPIO_LINE(x) (x)
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#ifndef __ASSEMBLY__
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extern int init_atu;
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extern int iop3xx_get_init_atu(void);
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#endif
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/*
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* IOP3XX processor registers
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*/
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#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
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#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfedfe000
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#define IOP3XX_PERIPHERAL_SIZE 0x00002000
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#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
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IOP3XX_PERIPHERAL_SIZE - 1)
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#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
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IOP3XX_PERIPHERAL_SIZE - 1)
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#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
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(IOP3XX_PERIPHERAL_PHYS_BASE\
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- IOP3XX_PERIPHERAL_VIRT_BASE))
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#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
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/* Address Translation Unit */
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#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
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#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
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#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
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#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
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#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
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#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
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#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
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#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
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#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
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#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
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#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
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#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
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#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
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#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
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#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
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#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
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#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
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#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
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#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
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#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
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#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
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#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
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#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
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#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
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#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
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#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
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#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
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#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
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#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
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#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
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#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
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#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
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#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
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#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
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#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
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#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
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#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
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#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
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#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
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#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
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#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
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#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
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#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
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#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
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#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
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#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
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#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
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#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
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#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
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#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
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#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
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#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
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#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
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#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
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#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
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#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
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#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
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#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14)
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#define IOP3XX_ATUCR_OUT_EN (1 << 1)
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#define IOP3XX_INIT_ATU_DEFAULT 0
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#define IOP3XX_INIT_ATU_DISABLE -1
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#define IOP3XX_INIT_ATU_ENABLE 1
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/* Messaging Unit */
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#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
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#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
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#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
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#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
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#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
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#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
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#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
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#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
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#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
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#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
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#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
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#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
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#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
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#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
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#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
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#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
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#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
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#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
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#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
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#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
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#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
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/* DMA Controller */
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#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
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(0x400 + (chan << 6)))
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#define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
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/* Peripheral bus interface */
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#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
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#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
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#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
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#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
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#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
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#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
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#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
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#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
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#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
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#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
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#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
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#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
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#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
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#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
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#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
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#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
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#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
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/* Peripheral performance monitoring unit */
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#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
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#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
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#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
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#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
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/* PERCR0 DOESN'T EXIST - index from 1! */
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#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
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/* Timers */
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#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
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#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
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#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
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#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
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#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
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#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
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#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
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#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
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#define IOP_TMR_EN 0x02
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#define IOP_TMR_RELOAD 0x04
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#define IOP_TMR_PRIVILEGED 0x08
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#define IOP_TMR_RATIO_1_1 0x00
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/* Watchdog timer definitions */
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#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
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#define IOP_WDTCR_EN 0xe1e1e1e1
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/* iop3xx does not support stopping the watchdog, so we just re-arm */
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#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM)
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#define IOP_WDTCR_DIS (IOP_WDTCR_EN)
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/* Application accelerator unit */
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#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
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#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
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/* I2C bus interface unit */
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#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
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#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
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#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
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#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
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#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
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#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
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#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
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#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
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#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
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#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
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/*
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* IOP3XX I/O and Mem space regions for PCI autoconfiguration
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*/
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#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
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#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000
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#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
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#define IOP3XX_PCI_LOWER_IO_BA 0x00000000
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/reboot.h>
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void iop3xx_map_io(void);
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void iop_init_cp6_handler(void);
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void iop_init_time(unsigned long tickrate);
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void iop3xx_restart(enum reboot_mode, const char *);
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2024-09-09 08:52:07 +00:00
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static inline u32 read_tmr0(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val));
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return val;
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}
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static inline void write_tmr0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
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}
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static inline void write_tmr1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
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}
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static inline u32 read_tcr0(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
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return val;
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}
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static inline void write_tcr0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val));
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}
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static inline u32 read_tcr1(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
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return val;
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}
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static inline void write_tcr1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val));
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}
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static inline void write_trr0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
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}
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static inline void write_trr1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
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}
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static inline void write_tisr(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
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}
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static inline u32 read_wdtcr(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
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return val;
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}
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static inline void write_wdtcr(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
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}
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extern unsigned long get_iop_tick_rate(void);
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/* only iop13xx has these registers, we define these to present a
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* common register interface for the iop_wdt driver.
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*/
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#define IOP_RCSR_WDT (0)
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static inline u32 read_rcsr(void)
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{
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return 0;
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}
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static inline void write_wdtsr(u32 val)
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{
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do { } while (0);
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}
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extern struct platform_device iop3xx_dma_0_channel;
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extern struct platform_device iop3xx_dma_1_channel;
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extern struct platform_device iop3xx_aau_channel;
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extern struct platform_device iop3xx_i2c0_device;
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extern struct platform_device iop3xx_i2c1_device;
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#endif
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#endif
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