2024-09-09 08:52:07 +00:00
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/*
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2024-09-09 08:57:42 +00:00
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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2024-09-09 08:52:07 +00:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2024-09-09 08:57:42 +00:00
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/dts-v1/;
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/* First 4KB has trampoline code for secondary cores. */
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/memreserve/ 0x00000000 0x0001000;
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#include "socfpga.dtsi"
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2024-09-09 08:52:07 +00:00
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2024-09-09 08:57:42 +00:00
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/ {
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soc {
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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mmc0: dwmmc0@ff704000 {
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num-slots = <1>;
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broken-cd;
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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};
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2024-09-09 08:52:07 +00:00
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2024-09-09 08:57:42 +00:00
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sysmgr@ffd08000 {
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cpu1-start-addr = <0xffd080c4>;
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};
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};
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};
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