M7350/kernel/arch/arm/boot/dts/qcom/msm8996-blsp.dtsi

/*
 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
/ {
	aliases {
		spi9 = &spi_9;
		spi10 = &spi_10;
		spi12 = &spi_12;
	};
};

&soc {
	blsp1_uart3: uart@7571000 { /* BLSP1 UART3 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x7571000 0x200>,
		    <0x7544000 0x2b000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart3>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 109 0
			    1 &intc 0 238 0
			    2 &tlmm 42 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xFD>;

		qcom,bam-tx-ep-pipe-index = <4>;
		qcom,bam-rx-ep-pipe-index = <5>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>,
		    <&clock_gcc clk_gcc_blsp1_ahb_clk>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart3_sleep>;
		pinctrl-1 = <&blsp1_uart3_active>;

		qcom,msm-bus,name = "buart3";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			    <86 512 0 0>,
			    <86 512 500 800>;
		status = "disabled";
	};


	blsp1_uart6: uart@7574000 { /* BLSP1 UART6 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x7574000 0x200>,
		    <0x7544000 0x2b000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart6>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 112 0
			    1 &intc 0 238 0
			    2 &tlmm 42 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xFD>;

		qcom,bam-tx-ep-pipe-index = <10>;
		qcom,bam-rx-ep-pipe-index = <11>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_uart6_apps_clk>,
		    <&clock_gcc clk_gcc_blsp1_ahb_clk>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart6_sleep>;
		pinctrl-1 = <&blsp1_uart6_active>;

		qcom,msm-bus,name = "buart6";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			    <86 512 0 0>,
			    <86 512 500 800>;
		status = "disabled";
	};

	spi_9: spi@75B7000 { /* BLSP2 QUP3 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x075B7000 0x600>,
		      <0x07584000 0x2b000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 103 0>, <0 239 0>;
		spi-max-frequency = <19200000>;
		qcom,infinite-mode = <0>;
		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <16>;
		qcom,bam-producer-pipe-index = <17>;
		qcom,master-id = <84>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_9_active>;
		pinctrl-1 = <&spi_9_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp2_qup3_spi_apps_clk>;
		status = "disabled";
	};

	spi_10: spi@75B8000 { /* BLSP2 QUP4 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x075B8000 0x600>,
		      <0x07584000 0x2b000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 104 0>, <0 239 0>;
		spi-max-frequency = <19200000>;
		qcom,infinite-mode = <0>;
		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <18>;
		qcom,bam-producer-pipe-index = <19>;
		qcom,master-id = <84>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_10_active>;
		pinctrl-1 = <&spi_10_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp2_qup4_spi_apps_clk>;
		status = "disabled";
	};

	spi_12: spi@75BA000 { /* BLSP2 QUP6 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x075BA000 0x600>,
		      <0x07584000 0x2b000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 106 0>, <0 239 0>;
		spi-max-frequency = <19200000>;
		qcom,infinite-mode = <0>;
		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <22>;
		qcom,bam-producer-pipe-index = <23>;
		qcom,master-id = <84>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_12_active>;
		pinctrl-1 = <&spi_12_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp2_qup6_spi_apps_clk>;
		status = "disabled";
	};
};