1864 lines
49 KiB
Plaintext
1864 lines
49 KiB
Plaintext
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/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/ {
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interrupt-parent = <&intc>;
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aliases {
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sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
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sdhc2 = &sdhc_2; /* SDC2 SD card slot */
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/* smdtty devices */
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smd0 = &smdtty_ds;
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smd1 = &smdtty_apps_fm;
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smd2 = &smdtty_apps_riva_bt_acl;
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smd3 = &smdtty_apps_riva_bt_cmd;
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smd5 = &smdtty_apps_riva_ant_cmd;
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smd6 = &smdtty_apps_riva_ant_data;
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smd7 = &smdtty_data1;
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smd8 = &smdtty_data4;
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smd11 = &smdtty_data11;
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smd21 = &smdtty_data21;
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smd36 = &smdtty_loopback;
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i2c0 = &i2c_0;
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i2c4 = &i2c_4;
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i2c5 = &i2c_5;
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i2c6 = &i2c_6;
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spi0 = &spi_0;
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spi5 = &spi_5;
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};
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memory {
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#address-cells = <2>;
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#size-cells = <2>;
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external_image_mem: external_image__region@0 {
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linux,reserve-contiguous-region;
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linux,reserve-region;
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linux,remove-completely;
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reg = <0x0 0x86000000 0x0 0x0800000>;
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label = "external_image_mem";
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};
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modem_adsp_mem: modem_adsp_region@0 {
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linux,reserve-contiguous-region;
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linux,reserve-region;
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linux,remove-completely;
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reg = <0x0 0x86800000 0x0 0x05500000>;
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label = "modem_adsp_mem";
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};
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peripheral_mem: pheripheral_region@0 {
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linux,reserve-contiguous-region;
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linux,reserve-region;
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linux,remove-completely;
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reg = <0x0 0x8bd00000 0x0 0x0600000>;
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label = "peripheral_mem";
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};
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venus_mem: venus_region@0 {
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linux,reserve-contiguous-region;
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linux,memory-limit = <0x90000000>;
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reg = <0 0 0 0x0500000>;
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label = "venus_mem";
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};
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secure_mem: secure_region@0 {
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linux,reserve-contiguous-region;
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reg = <0 0 0 0x6D00000>;
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label = "secure_mem";
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};
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qseecom_mem: qseecom_region@0 {
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linux,reserve-contiguous-region;
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reg = <0 0 0 0x1000000>;
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label = "qseecom_mem";
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};
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audio_mem: audio_region@0 {
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linux,reserve-contiguous-region;
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reg = <0 0 0 0x314000>;
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label = "audio_mem";
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};
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cont_splash_mem: splash_region@83000000 {
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linux,reserve-contiguous-region;
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linux,reserve-region;
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reg = <0x0 0x83000000 0x0 0x2000000>;
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label = "cont_splash_mem";
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};
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};
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soc: soc { };
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};
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#include "msm8939-ipcrouter.dtsi"
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#include "msm8939-ion.dtsi"
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#include "msm-gdsc-8916.dtsi"
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#include "msm8939-iommu.dtsi"
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#include "msm8939-bus.dtsi"
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#include "msm8939-mdss.dtsi"
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#include "msm8939-iommu-domains.dtsi"
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#include "msm8939-camera.dtsi"
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#include "msm8939-mdss-pll.dtsi"
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x0b000000 0x1000>,
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<0x0b002000 0x1000>;
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};
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restart@4ab000 {
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compatible = "qcom,pshold";
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reg = <0x4ab000 0x4>;
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reg-names = "pshold-base";
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};
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timer@b120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xb120000 0x1000>;
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clock-frequency = <19200000>;
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frame@b121000 {
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frame-number = <0>;
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interrupts = <0 8 0x4>,
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<0 7 0x4>;
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reg = <0xb121000 0x1000>,
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<0xb122000 0x1000>;
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};
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frame@b123000 {
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frame-number = <1>;
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interrupts = <0 9 0x4>;
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reg = <0xb123000 0x1000>;
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status = "disabled";
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};
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frame@b124000 {
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frame-number = <2>;
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interrupts = <0 10 0x4>;
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reg = <0xb124000 0x1000>;
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status = "disabled";
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};
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frame@b125000 {
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frame-number = <3>;
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interrupts = <0 11 0x4>;
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reg = <0xb125000 0x1000>;
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status = "disabled";
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};
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frame@b126000 {
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frame-number = <4>;
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interrupts = <0 12 0x4>;
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reg = <0xb126000 0x1000>;
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status = "disabled";
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};
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frame@b127000 {
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frame-number = <5>;
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interrupts = <0 13 0x4>;
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reg = <0xb127000 0x1000>;
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status = "disabled";
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};
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frame@b128000 {
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frame-number = <6>;
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interrupts = <0 14 0x4>;
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reg = <0xb128000 0x1000>;
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status = "disabled";
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};
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};
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qcom,sps {
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compatible = "qcom,msm_sps_4k";
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qcom,device-type = <3>;
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qcom,pipe-attr-ee;
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};
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qcom,ipc-spinlock@1905000 {
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compatible = "qcom,ipc-spinlock-sfpb";
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reg = <0x1905000 0x8000>;
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qcom,num-locks = <8>;
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};
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qcom,wdt@b017000 {
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compatible = "qcom,msm-watchdog";
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reg = <0xb017000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <0 3 0>, <0 4 0>;
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qcom,bark-time = <11000>;
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qcom,pet-time = <10000>;
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qcom,ipi-ping;
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};
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qcom,msm-rtb {
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compatible = "qcom,msm-rtb";
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qcom,rtb-size = <0x100000>;
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};
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rpm_bus: qcom,rpm-smd {
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compatible = "qcom,rpm-smd";
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rpm-channel-name = "rpm_requests";
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rpm-channel-type = <15>; /* SMD_APPS_RPM */
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};
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bam_dmux: qcom,bam_dmux@4044000 {
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compatible = "qcom,bam_dmux";
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reg = <0x4044000 0x19000>;
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interrupts = <0 29 1>;
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qcom,rx-ring-size = <32>;
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qcom,max-rx-mtu = <4096>;
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};
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qcom,smdtty {
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compatible = "qcom,smdtty";
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smdtty_apps_fm: qcom,smdtty-apps-fm {
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qcom,smdtty-remote = "wcnss";
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qcom,smdtty-port-name = "APPS_FM";
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};
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smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl {
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qcom,smdtty-remote = "wcnss";
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qcom,smdtty-port-name = "APPS_RIVA_BT_ACL";
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};
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smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd {
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qcom,smdtty-remote = "wcnss";
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qcom,smdtty-port-name = "APPS_RIVA_BT_CMD";
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};
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smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd {
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qcom,smdtty-remote = "wcnss";
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qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD";
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};
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smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data {
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qcom,smdtty-remote = "wcnss";
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qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA";
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};
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smdtty_data1: qcom,smdtty-data1 {
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qcom,smdtty-remote = "modem";
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qcom,smdtty-port-name = "DATA1";
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};
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smdtty_data4: qcom,smdtty-data4 {
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qcom,smdtty-remote = "modem";
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qcom,smdtty-port-name = "DATA4";
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};
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smdtty_data11: qcom,smdtty-data11 {
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qcom,smdtty-remote = "modem";
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qcom,smdtty-port-name = "DATA11";
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};
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smdtty_data21: qcom,smdtty-data21 {
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qcom,smdtty-remote = "modem";
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qcom,smdtty-port-name = "DATA21";
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};
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smdtty_loopback: smdtty-loopback {
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qcom,smdtty-remote = "modem";
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qcom,smdtty-port-name = "LOOPBACK";
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qcom,smdtty-dev-name = "LOOPBACK_TTY";
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};
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smdtty_ds: qcom,smdtty-ds {
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qcom,smdtty-remote = "modem";
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qcom,smdtty-port-name = "DS";
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};
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};
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qcom,smdpkt {
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compatible = "qcom,smdpkt";
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qcom,smdpkt-data5-cntl {
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qcom,smdpkt-remote = "modem";
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qcom,smdpkt-port-name = "DATA5_CNTL";
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qcom,smdpkt-dev-name = "smdcntl0";
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};
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qcom,smdpkt-data6-cntl {
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qcom,smdpkt-remote = "modem";
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qcom,smdpkt-port-name = "DATA6_CNTL";
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qcom,smdpkt-dev-name = "smdcntl1";
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};
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qcom,smdpkt-data7-cntl {
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qcom,smdpkt-remote = "modem";
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qcom,smdpkt-port-name = "DATA7_CNTL";
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qcom,smdpkt-dev-name = "smdcntl2";
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};
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qcom,smdpkt-data8-cntl {
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qcom,smdpkt-remote = "modem";
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qcom,smdpkt-port-name = "DATA8_CNTL";
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qcom,smdpkt-dev-name = "smdcntl3";
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};
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qcom,smdpkt-data9-cntl {
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qcom,smdpkt-remote = "modem";
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qcom,smdpkt-port-name = "DATA9_CNTL";
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qcom,smdpkt-dev-name = "smdcntl4";
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};
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qcom,smdpkt-data12-cntl {
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qcom,smdpkt-remote = "modem";
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qcom,smdpkt-port-name = "DATA12_CNTL";
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qcom,smdpkt-dev-name = "smdcntl5";
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};
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qcom,smdpkt-data13-cntl {
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qcom,smdpkt-remote = "modem";
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qcom,smdpkt-port-name = "DATA13_CNTL";
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qcom,smdpkt-dev-name = "smdcntl6";
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};
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qcom,smdpkt-data14-cntl {
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qcom,smdpkt-remote = "modem";
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qcom,smdpkt-port-name = "DATA14_CNTL";
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qcom,smdpkt-dev-name = "smdcntl7";
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};
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qcom,smdpkt-data15-cntl {
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qcom,smdpkt-remote = "modem";
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qcom,smdpkt-port-name = "DATA15_CNTL";
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qcom,smdpkt-dev-name = "smdcntl9";
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};
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qcom,smdpkt-data16-cntl {
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qcom,smdpkt-remote = "modem";
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qcom,smdpkt-port-name = "DATA16_CNTL";
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qcom,smdpkt-dev-name = "smdcntl10";
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};
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qcom,smdpkt-data17-cntl {
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qcom,smdpkt-remote = "modem";
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qcom,smdpkt-port-name = "DATA17_CNTL";
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qcom,smdpkt-dev-name = "smdcntl11";
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};
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qcom,smdpkt-data22 {
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qcom,smdpkt-remote = "modem";
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|
qcom,smdpkt-port-name = "DATA22";
|
||
|
|
qcom,smdpkt-dev-name = "smd22";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,smdpkt-data23-cntl {
|
||
|
|
qcom,smdpkt-remote = "modem";
|
||
|
|
qcom,smdpkt-port-name = "DATA23_CNTL";
|
||
|
|
qcom,smdpkt-dev-name = "smdcnt_rev0";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,smdpkt-data24-cntl {
|
||
|
|
qcom,smdpkt-remote = "modem";
|
||
|
|
qcom,smdpkt-port-name = "DATA24_CNTL";
|
||
|
|
qcom,smdpkt-dev-name = "smdcnt_rev1";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,smdpkt-data25-cntl {
|
||
|
|
qcom,smdpkt-remote = "modem";
|
||
|
|
qcom,smdpkt-port-name = "DATA25_CNTL";
|
||
|
|
qcom,smdpkt-dev-name = "smdcnt_rev2";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,smdpkt-data26-cntl {
|
||
|
|
qcom,smdpkt-remote = "modem";
|
||
|
|
qcom,smdpkt-port-name = "DATA26_CNTL";
|
||
|
|
qcom,smdpkt-dev-name = "smdcnt_rev3";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,smdpkt-data27-cntl {
|
||
|
|
qcom,smdpkt-remote = "modem";
|
||
|
|
qcom,smdpkt-port-name = "DATA27_CNTL";
|
||
|
|
qcom,smdpkt-dev-name = "smdcnt_rev4";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,smdpkt-data28-cntl {
|
||
|
|
qcom,smdpkt-remote = "modem";
|
||
|
|
qcom,smdpkt-port-name = "DATA28_CNTL";
|
||
|
|
qcom,smdpkt-dev-name = "smdcnt_rev5";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,smdpkt-data29-cntl {
|
||
|
|
qcom,smdpkt-remote = "modem";
|
||
|
|
qcom,smdpkt-port-name = "DATA29_CNTL";
|
||
|
|
qcom,smdpkt-dev-name = "smdcnt_rev6";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,smdpkt-data30-cntl {
|
||
|
|
qcom,smdpkt-remote = "modem";
|
||
|
|
qcom,smdpkt-port-name = "DATA30_CNTL";
|
||
|
|
qcom,smdpkt-dev-name = "smdcnt_rev7";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,smdpkt-data31-cntl {
|
||
|
|
qcom,smdpkt-remote = "modem";
|
||
|
|
qcom,smdpkt-port-name = "DATA31_CNTL";
|
||
|
|
qcom,smdpkt-dev-name = "smdcnt_rev8";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,smdpkt-data40-cntl {
|
||
|
|
qcom,smdpkt-remote = "modem";
|
||
|
|
qcom,smdpkt-port-name = "DATA40_CNTL";
|
||
|
|
qcom,smdpkt-dev-name = "smdcntl8";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,smdpkt-apr-apps2 {
|
||
|
|
qcom,smdpkt-remote = "modem";
|
||
|
|
qcom,smdpkt-port-name = "apr_apps2";
|
||
|
|
qcom,smdpkt-dev-name = "apr_apps2";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,smdpkt-loopback {
|
||
|
|
qcom,smdpkt-remote = "modem";
|
||
|
|
qcom,smdpkt-port-name = "LOOPBACK";
|
||
|
|
qcom,smdpkt-dev-name = "smd_pkt_loopback";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,iris-fm {
|
||
|
|
compatible = "qcom,iris_fm";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,wcnss-wlan@0a000000 {
|
||
|
|
compatible = "qcom,wcnss_wlan";
|
||
|
|
reg = <0x0a000000 0x280000>,
|
||
|
|
<0xb011008 0x04>,
|
||
|
|
<0x0a21b000 0x3000>,
|
||
|
|
<0x03204000 0x00000100>,
|
||
|
|
<0x03200800 0x00000200>,
|
||
|
|
<0x0A100400 0x00000200>,
|
||
|
|
<0x0A205050 0x00000200>,
|
||
|
|
<0x0A219000 0x00000020>,
|
||
|
|
<0x0A080488 0x00000008>,
|
||
|
|
<0x0A080fb0 0x00000008>,
|
||
|
|
<0x0A08040c 0x00000008>,
|
||
|
|
<0x0A0120a8 0x00000008>,
|
||
|
|
<0x0A012448 0x00000008>,
|
||
|
|
<0x0A080c00 0x00000001>;
|
||
|
|
|
||
|
|
reg-names = "wcnss_mmio", "wcnss_fiq",
|
||
|
|
"pronto_phy_base", "riva_phy_base",
|
||
|
|
"riva_ccu_base", "pronto_a2xb_base",
|
||
|
|
"pronto_ccpu_base", "pronto_saw2_base",
|
||
|
|
"wlan_tx_phy_aborts","wlan_brdg_err_source",
|
||
|
|
"wlan_tx_status", "alarms_txctl",
|
||
|
|
"alarms_tactl", "pronto_mcu_base";
|
||
|
|
|
||
|
|
interrupts = <0 145 0 0 146 0>;
|
||
|
|
interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
|
||
|
|
|
||
|
|
qcom,pronto-vddmx-supply = <&pm8916_l3>;
|
||
|
|
qcom,pronto-vddcx-supply = <&pm8916_s2_corner>;
|
||
|
|
qcom,pronto-vddpx-supply = <&pm8916_l7>;
|
||
|
|
qcom,iris-vddxo-supply = <&pm8916_l7>;
|
||
|
|
qcom,iris-vddrfa-supply = <&pm8916_s3>;
|
||
|
|
qcom,iris-vddpa-supply = <&pm8916_l9>;
|
||
|
|
qcom,iris-vdddig-supply = <&pm8916_l5>;
|
||
|
|
|
||
|
|
qcom,iris-vddxo-voltage-level = <1800000 0 1800000>;
|
||
|
|
qcom,iris-vddrfa-voltage-level = <1300000 0 1300000>;
|
||
|
|
qcom,iris-vddpa-voltage-level = <3300000 0 3300000>;
|
||
|
|
qcom,iris-vdddig-voltage-level = <1800000 0 1800000>;
|
||
|
|
|
||
|
|
qcom,vddmx-voltage-level = <7 0 7>;
|
||
|
|
qcom,vddcx-voltage-level = <5 1 7>;
|
||
|
|
qcom,vddpx-voltage-level = <1800000 0 1800000>;
|
||
|
|
|
||
|
|
qcom,iris-vddxo-current = <10000>;
|
||
|
|
qcom,iris-vddrfa-current = <100000>;
|
||
|
|
qcom,iris-vddpa-current = <515000>;
|
||
|
|
qcom,iris-vdddig-current = <10000>;
|
||
|
|
|
||
|
|
qcom,pronto-vddmx-current = <0>;
|
||
|
|
qcom,pronto-vddcx-current = <0>;
|
||
|
|
qcom,pronto-vddpx-current = <0>;
|
||
|
|
|
||
|
|
pinctrl-names = "wcnss_default", "wcnss_sleep",
|
||
|
|
"wcnss_gpio_default";
|
||
|
|
pinctrl-0 = <&wcnss_default>;
|
||
|
|
pinctrl-1 = <&wcnss_sleep>;
|
||
|
|
pinctrl-2 = <&wcnss_gpio_default>;
|
||
|
|
gpios = <&msm_gpio 40 0>, <&msm_gpio 41 0>, <&msm_gpio 42 0>,
|
||
|
|
<&msm_gpio 43 0>, <&msm_gpio 44 0>;
|
||
|
|
|
||
|
|
clocks = <&clock_rpm clk_xo_wlan_clk>,
|
||
|
|
<&clock_rpm clk_rf_clk2>,
|
||
|
|
<&clock_debug clk_gcc_debug_mux>,
|
||
|
|
<&clock_gcc clk_wcnss_m_clk>;
|
||
|
|
clock-names = "xo", "rf_clk", "measure", "wcnss_debug";
|
||
|
|
|
||
|
|
qcom,has-autodetect-xo;
|
||
|
|
qcom,has-pronto-hw;
|
||
|
|
qcom,wcnss-adc_tm = <&pm8916_adc_tm>;
|
||
|
|
};
|
||
|
|
|
||
|
|
tsens: tsens@4a8000 {
|
||
|
|
compatible = "qcom,msm8939-tsens";
|
||
|
|
reg = <0x4a8000 0x2000>,
|
||
|
|
<0x5c000 0x1000>;
|
||
|
|
reg-names = "tsens_physical", "tsens_eeprom_physical";
|
||
|
|
interrupts = <0 184 0>;
|
||
|
|
interrupt-names = "tsens-upper-lower";
|
||
|
|
qcom,sensors = <9>;
|
||
|
|
qcom,slope = <2911 2789 2906 2763 2922 2867 2833 2838 2840>;
|
||
|
|
qcom,sensor-id = <0 1 2 3 5 6 7 8 9>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-thermal {
|
||
|
|
compatible = "qcom,msm-thermal";
|
||
|
|
qcom,sensor-id = <5>;
|
||
|
|
qcom,poll-ms = <250>;
|
||
|
|
qcom,limit-temp = <60>;
|
||
|
|
qcom,temp-hysteresis = <10>;
|
||
|
|
qcom,freq-step = <2>;
|
||
|
|
qcom,freq-control-mask = <0xff>;
|
||
|
|
qcom,core-limit-temp = <80>;
|
||
|
|
qcom,core-temp-hysteresis = <10>;
|
||
|
|
qcom,core-control-mask = <0xfe>;
|
||
|
|
qcom,hotplug-temp = <105>;
|
||
|
|
qcom,hotplug-temp-hysteresis = <15>;
|
||
|
|
qcom,cpu-sensors = "tsens_tz_sensor5", "tsens_tz_sensor6",
|
||
|
|
"tsens_tz_sensor7", "tsens_tz_sensor8",
|
||
|
|
"tsens_tz_sensor9", "tsens_tz_sensor9",
|
||
|
|
"tsens_tz_sensor9", "tsens_tz_sensor9";
|
||
|
|
qcom,freq-mitigation-temp = <105>;
|
||
|
|
qcom,freq-mitigation-temp-hysteresis = <15>;
|
||
|
|
qcom,freq-mitigation-value = <400000>;
|
||
|
|
qcom,freq-mitigation-control-mask = <0x01>;
|
||
|
|
qcom,therm-reset-temp = <115>;
|
||
|
|
qcom,online-hotplug-core;
|
||
|
|
qcom,synchronous-cluster-id = <0 1>;
|
||
|
|
qcom,synchronous-cluster-map = <1 4 &CPU0 &CPU1 &CPU2 &CPU3>,
|
||
|
|
<0 4 &CPU4 &CPU5 &CPU6 &CPU7>;
|
||
|
|
qcom,vdd-restriction-temp = <5>;
|
||
|
|
qcom,vdd-restriction-temp-hysteresis = <10>;
|
||
|
|
vdd-dig-supply = <&pm8916_s2_floor_corner>;
|
||
|
|
|
||
|
|
qcom,vdd-dig-rstr{
|
||
|
|
qcom,vdd-rstr-reg = "vdd-dig";
|
||
|
|
qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */
|
||
|
|
qcom,min-level = <1>; /* No Request */
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,vdd-apps-rstr{
|
||
|
|
qcom,vdd-rstr-reg = "vdd-apps";
|
||
|
|
qcom,levels = <998400>;
|
||
|
|
qcom,freq-req;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,bcl {
|
||
|
|
compatible = "qcom,bcl";
|
||
|
|
qcom,bcl-no-bms;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,memshare {
|
||
|
|
compatible = "qcom,memshare";
|
||
|
|
|
||
|
|
qcom,client_1 {
|
||
|
|
compatible = "qcom,memshare-peripheral";
|
||
|
|
qcom,peripheral-size = <2097152>;
|
||
|
|
label = "modem";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
slim_msm: slim@77c0000 {
|
||
|
|
cell-index = <1>;
|
||
|
|
compatible = "qcom,slim-ngd";
|
||
|
|
reg = <0x77c0000 0x2C000>,
|
||
|
|
<0x7784000 0x2A000>;
|
||
|
|
reg-names = "slimbus_physical", "slimbus_bam_physical";
|
||
|
|
interrupts = <0 163 0>, <0 180 0>;
|
||
|
|
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
|
||
|
|
qcom,apps-ch-pipes = <0x600000>;
|
||
|
|
qcom,ea-pc = <0x140>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
clock_rpm: qcom,rpmcc@1874000 {
|
||
|
|
compatible = "qcom,rpmcc-8936";
|
||
|
|
reg = <0x1874000 0x4>;
|
||
|
|
reg-names = "cc_base";
|
||
|
|
#clock-cells = <1>;
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
clock_gcc: qcom,gcc@1800000 {
|
||
|
|
compatible = "qcom,gcc-8936";
|
||
|
|
reg = <0x1800000 0x80000>,
|
||
|
|
<0xb116000 0x00040>,
|
||
|
|
<0xb016000 0x00040>,
|
||
|
|
<0xb1d0000 0x00040>;
|
||
|
|
reg-names = "cc_base", "apcs_c0_base",
|
||
|
|
"apcs_c1_base", "apcs_cci_base";
|
||
|
|
vdd_dig-supply = <&pm8916_s2_corner>;
|
||
|
|
vdd_sr2_dig-supply = <&pm8916_s2_corner_ao>;
|
||
|
|
vdd_sr2_pll-supply = <&pm8916_l7_ao>;
|
||
|
|
vdd_hf_dig-supply = <&pm8916_s2_corner_ao>;
|
||
|
|
vdd_hf_pll-supply = <&pm8916_l7_ao>;
|
||
|
|
clocks = <&clock_rpm clk_xo_clk_src>,
|
||
|
|
<&clock_rpm clk_xo_a_clk_src>;
|
||
|
|
clock-names = "xo", "xo_a";
|
||
|
|
#clock-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
clock_gcc_mdss: qcom,gcc-mdss@1a98300 {
|
||
|
|
compatible = "qcom,gcc-mdss-8936";
|
||
|
|
clocks = <&mdss_dsi0_pll clk_pixel_clk_src>,
|
||
|
|
<&mdss_dsi0_pll clk_byte_clk_src>,
|
||
|
|
<&mdss_dsi0_pll clk_pixel_clk_src>,
|
||
|
|
<&mdss_dsi0_pll clk_byte_clk_src>;
|
||
|
|
clock-names = "pclk0_src", "byte0_src", "pclk1_src",
|
||
|
|
"byte1_src";
|
||
|
|
#clock-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
clock_debug: qcom,cc-debug@1874000 {
|
||
|
|
compatible = "qcom,cc-debug-8936";
|
||
|
|
reg = <0x1874000 0x4>;
|
||
|
|
reg-names = "cc_base";
|
||
|
|
clocks = <&clock_rpm clk_rpm_debug_mux>;
|
||
|
|
clock-names = "rpm_debug_mux";
|
||
|
|
#clock-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,cpu-bwmon {
|
||
|
|
compatible = "qcom,bimc-bwmon";
|
||
|
|
reg = <0x408000 0x300>, <0x401000 0x200>;
|
||
|
|
reg-names = "base", "global_base";
|
||
|
|
interrupts = <0 183 4>;
|
||
|
|
qcom,mport = <0>;
|
||
|
|
qcom,target-dev = <&cpubw>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom_tzlog: tz-log@8600720 {
|
||
|
|
compatible = "qcom,tz-log";
|
||
|
|
reg = <0x08600720 0x1000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom_rng: qrng@22000 {
|
||
|
|
compatible = "qcom,msm-rng";
|
||
|
|
reg = <0x22000 0x200>;
|
||
|
|
qcom,msm-rng-iface-clk;
|
||
|
|
qcom,msm-bus,name = "msm-rng-noc";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<1 618 0 0>, /* No vote */
|
||
|
|
<1 618 0 800>; /* 100 MB/s */
|
||
|
|
clocks = <&clock_gcc clk_gcc_prng_ahb_clk>;
|
||
|
|
clock-names = "iface_clk";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-adsp-loader {
|
||
|
|
compatible = "qcom,adsp-loader";
|
||
|
|
qcom,adsp-state = <0>;
|
||
|
|
qcom,proc-img-to-load = "modem";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom_crypto: qcrypto@720000 {
|
||
|
|
compatible = "qcom,qcrypto";
|
||
|
|
reg = <0x720000 0x20000>,
|
||
|
|
<0x704000 0x20000>;
|
||
|
|
reg-names = "crypto-base","crypto-bam-base";
|
||
|
|
interrupts = <0 207 0>;
|
||
|
|
qcom,bam-pipe-pair = <2>;
|
||
|
|
qcom,ce-hw-instance = <0>;
|
||
|
|
qcom,ce-device = <0>;
|
||
|
|
qcom,clk-mgmt-sus-res;
|
||
|
|
qcom,msm-bus,name = "qcrypto-noc";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<55 512 0 0>,
|
||
|
|
<55 512 393600 800000>; /* 49.2MHz & 100MHz */
|
||
|
|
clocks = <&clock_gcc clk_crypto_clk_src>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_axi_clk>;
|
||
|
|
clock-names = "core_clk_src", "core_clk",
|
||
|
|
"iface_clk", "bus_clk";
|
||
|
|
qcom,use-sw-aes-cbc-ecb-ctr-algo;
|
||
|
|
qcom,use-sw-aes-xts-algo;
|
||
|
|
qcom,use-sw-aes-ccm-algo;
|
||
|
|
qcom,use-sw-ahash-algo;
|
||
|
|
status = "disabled";
|
||
|
|
qcom,ce-opp-freq = <100000000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom_cedev: qcedev@720000 {
|
||
|
|
compatible = "qcom,qcedev";
|
||
|
|
reg = <0x720000 0x20000>,
|
||
|
|
<0x704000 0x20000>;
|
||
|
|
reg-names = "crypto-base","crypto-bam-base";
|
||
|
|
interrupts = <0 207 0>;
|
||
|
|
qcom,bam-pipe-pair = <1>;
|
||
|
|
qcom,ce-hw-instance = <0>;
|
||
|
|
qcom,ce-device = <0>;
|
||
|
|
qcom,ce-hw-shared;
|
||
|
|
qcom,msm-bus,name = "qcedev-noc";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<55 512 0 0>,
|
||
|
|
<55 512 393600 800000>; /* 49.2MHz & 100MHz */
|
||
|
|
clocks = <&clock_gcc clk_crypto_clk_src>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_axi_clk>;
|
||
|
|
clock-names = "core_clk_src", "core_clk",
|
||
|
|
"iface_clk", "bus_clk";
|
||
|
|
status = "disabled";
|
||
|
|
qcom,ce-opp-freq = <100000000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom_seecom: qseecom@86000000 {
|
||
|
|
compatible = "qcom,qseecom";
|
||
|
|
reg = <0x86000000 0x300000>;
|
||
|
|
reg-names = "secapp-region";
|
||
|
|
qcom,disk-encrypt-pipe-pair = <2>;
|
||
|
|
qcom,hlos-ce-hw-instance = <0>;
|
||
|
|
qcom,qsee-ce-hw-instance = <0>;
|
||
|
|
qcom,msm-bus,name = "qseecom-noc";
|
||
|
|
qcom,msm-bus,num-cases = <4>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,support-bus-scaling;
|
||
|
|
qcom,support-fde;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<55 512 0 0>,
|
||
|
|
<55 512 0 0>,
|
||
|
|
<55 512 120000 1200000>,
|
||
|
|
<55 512 393600 3936000>;
|
||
|
|
clocks = <&clock_gcc clk_crypto_clk_src>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_axi_clk>;
|
||
|
|
clock-names = "core_clk_src", "core_clk",
|
||
|
|
"iface_clk", "bus_clk";
|
||
|
|
status = "disabled";
|
||
|
|
qcom,ce-opp-freq = <100000000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,usbbam@78c4000 {
|
||
|
|
compatible = "qcom,usb-bam-msm";
|
||
|
|
reg = <0x78c4000 0x15000>;
|
||
|
|
interrupts = <0 135 0>;
|
||
|
|
qcom,bam-type = <1>;
|
||
|
|
qcom,usb-bam-num-pipes = <2>;
|
||
|
|
qcom,usb-bam-fifo-baseaddr = <0x08603800>;
|
||
|
|
qcom,ignore-core-reset-ack;
|
||
|
|
qcom,disable-clk-gating;
|
||
|
|
qcom,reset-bam-on-connect;
|
||
|
|
|
||
|
|
qcom,pipe0 {
|
||
|
|
label = "hsusb-qdss-in-0";
|
||
|
|
qcom,usb-bam-mem-type = <2>;
|
||
|
|
qcom,dir = <1>;
|
||
|
|
qcom,pipe-num = <0>;
|
||
|
|
qcom,peer-bam = <0>;
|
||
|
|
qcom,peer-bam-physical-address = <0x884000>;
|
||
|
|
qcom,src-bam-pipe-index = <0>;
|
||
|
|
qcom,dst-bam-pipe-index = <0>;
|
||
|
|
qcom,data-fifo-offset = <0x0>;
|
||
|
|
qcom,data-fifo-size = <0x600>;
|
||
|
|
qcom,descriptor-fifo-offset = <0x600>;
|
||
|
|
qcom,descriptor-fifo-size = <0x200>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
usb_otg: usb@78d9000 {
|
||
|
|
compatible = "qcom,hsusb-otg";
|
||
|
|
|
||
|
|
reg = <0x78d9000 0x400>;
|
||
|
|
interrupts = <0 134 0>,<0 140 0>;
|
||
|
|
interrupt-names = "core_irq", "async_irq";
|
||
|
|
|
||
|
|
hsusb_vdd_dig-supply = <&pm8916_s2_corner>;
|
||
|
|
HSUSB_1p8-supply = <&pm8916_l7>;
|
||
|
|
HSUSB_3p3-supply = <&pm8916_l13>;
|
||
|
|
qcom,vdd-voltage-level = <1 5 7>;
|
||
|
|
|
||
|
|
qcom,hsusb-otg-phy-init-seq =
|
||
|
|
<0x44 0x80 0x6B 0x81 0x24 0x82 0x13 0x83 0xffffffff>;
|
||
|
|
qcom,hsusb-otg-phy-type = <2>;
|
||
|
|
qcom,hsusb-otg-mode = <1>;
|
||
|
|
qcom,hsusb-otg-otg-control = <2>;
|
||
|
|
qcom,hsusb-otg-disable-reset;
|
||
|
|
qcom,dp-manual-pullup;
|
||
|
|
qcom,hsusb-otg-mpm-dpsehv-int = <49>;
|
||
|
|
qcom,hsusb-otg-mpm-dmsehv-int = <58>;
|
||
|
|
qcom,usbin-vadc = <&pm8916_vadc>;
|
||
|
|
|
||
|
|
qcom,msm-bus,name = "usb2";
|
||
|
|
qcom,msm-bus,num-cases = <3>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<87 512 0 0>,
|
||
|
|
<87 512 80000 0>,
|
||
|
|
<87 512 6000 6000>;
|
||
|
|
clocks = <&clock_gcc clk_gcc_usb_hs_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_usb_hs_system_clk>,
|
||
|
|
<&clock_gcc clk_gcc_usb2a_phy_sleep_clk>,
|
||
|
|
<&clock_rpm clk_bimc_usb_a_clk>,
|
||
|
|
<&clock_rpm clk_snoc_usb_a_clk>,
|
||
|
|
<&clock_rpm clk_pcnoc_usb_a_clk>,
|
||
|
|
<&clock_rpm clk_xo_otg_clk>;
|
||
|
|
clock-names = "iface_clk", "core_clk", "sleep_clk",
|
||
|
|
"bimc_clk", "snoc_clk", "pcnoc_clk",
|
||
|
|
"xo";
|
||
|
|
qcom,bus-clk-rate = <331200000 200000000 100000000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
android_usb: android_usb@086000c8 {
|
||
|
|
compatible = "qcom,android-usb";
|
||
|
|
reg = <0x086000c8 0xc8>;
|
||
|
|
qcom,pm-qos-latency = <2 1001 12701>;
|
||
|
|
qcom,android-usb-uicc-nluns = /bits/ 8 <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
uicc: qcom,ehci-host@79c0000 {
|
||
|
|
compatible = "qcom,ehci-uicc-host";
|
||
|
|
reg = <0x79c0000 0x400>;
|
||
|
|
interrupts = <0 132 0>;
|
||
|
|
|
||
|
|
clocks = <&clock_gcc clk_gcc_usb_fs_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_usb_fs_system_clk>,
|
||
|
|
<&clock_gcc clk_gcc_usb_fs_ic_clk>;
|
||
|
|
clock-names = "iface_clk", "core_clk", "alt_core_clk";
|
||
|
|
|
||
|
|
pinctrl-names = "uicc_active", "uicc_sleep";
|
||
|
|
pinctrl-0 = <&uicc_active>;
|
||
|
|
pinctrl-1 = <&uicc_sleep>;
|
||
|
|
|
||
|
|
qcom,msm-bus,name = "uicc";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<93 512 0 0>,
|
||
|
|
<93 512 12000 192000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp1_uart2: serial@78b0000 {
|
||
|
|
compatible = "qcom,msm-lsuart-v14", "qcom,msm-uartdm-v1.4",
|
||
|
|
"qcom,msm-uartdm";
|
||
|
|
reg = <0x78b0000 0x200>;
|
||
|
|
interrupts = <0 108 0>;
|
||
|
|
status = "disabled";
|
||
|
|
clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
|
||
|
|
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
|
||
|
|
clock-names = "core", "iface";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c_6: i2c@78ba000 { /* BLSP1 QUP6 */
|
||
|
|
compatible = "qcom,i2c-msm-v2";
|
||
|
|
#address-cells=<1>;
|
||
|
|
#size-cells=<0>;
|
||
|
|
cell-index = <6>;
|
||
|
|
reg-names = "qup_phys_addr", "bam_phys_addr";
|
||
|
|
reg = <0x78ba000 0x1000>,
|
||
|
|
<0x7884000 0x23000>;
|
||
|
|
interrupt-names = "qup_irq", "bam_irq";
|
||
|
|
interrupts = <0 100 0>, <0 238 0>;
|
||
|
|
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_blsp1_qup6_i2c_apps_clk>;
|
||
|
|
clock-names = "iface_clk", "core_clk";
|
||
|
|
qcom,clk-freq-out = <400000>;
|
||
|
|
qcom,clk-freq-in = <19200000>;
|
||
|
|
pinctrl-names = "i2c_active", "i2c_sleep";
|
||
|
|
pinctrl-0 = <&i2c_6_active>;
|
||
|
|
pinctrl-1 = <&i2c_6_sleep>;
|
||
|
|
qcom,noise-rjct-scl = <0>;
|
||
|
|
qcom,noise-rjct-sda = <0>;
|
||
|
|
qcom,bam-pipe-idx-cons = <14>;
|
||
|
|
qcom,bam-pipe-idx-prod = <15>;
|
||
|
|
qcom,master-id = <86>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c_0: i2c@78b6000 { /* BLSP1 QUP2 */
|
||
|
|
compatible = "qcom,i2c-msm-v2";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg-names = "qup_phys_addr", "bam_phys_addr";
|
||
|
|
reg = <0x78b6000 0x600>,
|
||
|
|
<0x7884000 0x23000>;
|
||
|
|
interrupt-names = "qup_irq", "bam_irq";
|
||
|
|
interrupts = <0 96 0>, <0 238 0>;
|
||
|
|
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;
|
||
|
|
clock-names = "iface_clk", "core_clk";
|
||
|
|
qcom,clk-freq-out = <100000>;
|
||
|
|
qcom,clk-freq-in = <19200000>;
|
||
|
|
pinctrl-names = "i2c_active", "i2c_sleep";
|
||
|
|
pinctrl-0 = <&i2c_0_active>;
|
||
|
|
pinctrl-1 = <&i2c_0_sleep>;
|
||
|
|
qcom,noise-rjct-scl = <0>;
|
||
|
|
qcom,noise-rjct-sda = <0>;
|
||
|
|
qcom,bam-pipe-idx-cons = <6>;
|
||
|
|
qcom,bam-pipe-idx-prod = <7>;
|
||
|
|
qcom,master-id = <86>;
|
||
|
|
};
|
||
|
|
|
||
|
|
spi_0: spi@78b7000 { /* BLSP1 QUP3 */
|
||
|
|
compatible = "qcom,spi-qup-v2";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg-names = "spi_physical", "spi_bam_physical";
|
||
|
|
reg = <0x78b7000 0x600>,
|
||
|
|
<0x7884000 0x23000>;
|
||
|
|
interrupt-names = "spi_irq", "spi_bam_irq";
|
||
|
|
interrupts = <0 97 0>, <0 238 0>;
|
||
|
|
spi-max-frequency = <19200000>;
|
||
|
|
pinctrl-names = "spi_default", "spi_sleep";
|
||
|
|
pinctrl-0 = <&spi0_default &spi0_cs0_active>;
|
||
|
|
pinctrl-1 = <&spi0_sleep &spi0_cs0_sleep>;
|
||
|
|
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>;
|
||
|
|
clock-names = "iface_clk", "core_clk";
|
||
|
|
qcom,infinite-mode = <0>;
|
||
|
|
qcom,use-bam;
|
||
|
|
qcom,use-pinctrl;
|
||
|
|
qcom,ver-reg-exists;
|
||
|
|
qcom,bam-consumer-pipe-index = <8>;
|
||
|
|
qcom,bam-producer-pipe-index = <9>;
|
||
|
|
qcom,master-id = <86>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c_4: i2c@78b8000 { /* BLSP1 QUP4 */
|
||
|
|
compatible = "qcom,i2c-msm-v2";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg-names = "qup_phys_addr", "bam_phys_addr";
|
||
|
|
reg = <0x78b8000 0x1000>,
|
||
|
|
<0x7884000 0x23000>;
|
||
|
|
interrupt-names = "qup_irq", "bam_irq";
|
||
|
|
interrupts = <0 98 0>, <0 238 0>;
|
||
|
|
qcom,clk-freq-out = <100000>;
|
||
|
|
qcom,clk-freq-in = <19200000>;
|
||
|
|
clock-names = "iface_clk", "core_clk";
|
||
|
|
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>;
|
||
|
|
|
||
|
|
pinctrl-names = "i2c_active", "i2c_sleep";
|
||
|
|
pinctrl-0 = <&i2c_4_active>;
|
||
|
|
pinctrl-1 = <&i2c_4_sleep>;
|
||
|
|
qcom,noise-rjct-scl = <0>;
|
||
|
|
qcom,noise-rjct-sda = <0>;
|
||
|
|
qcom,bam-pipe-idx-cons = <10>;
|
||
|
|
qcom,bam-pipe-idx-prod = <11>;
|
||
|
|
qcom,master-id = <86>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c_5: i2c@78b9000 { /* BLSP1 QUP5 */
|
||
|
|
compatible = "qcom,i2c-msm-v2";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg-names = "qup_phys_addr", "bam_phys_addr";
|
||
|
|
reg = <0x78b9000 0x600>,
|
||
|
|
<0x7884000 0x23000>;
|
||
|
|
interrupt-names = "qup_irq", "bam_irq";
|
||
|
|
interrupts = <0 99 0>, <0 238 0>;
|
||
|
|
qcom,clk-freq-out = <100000>;
|
||
|
|
qcom,clk-freq-in = <19200000>;
|
||
|
|
clock-names = "iface_clk", "core_clk";
|
||
|
|
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>;
|
||
|
|
|
||
|
|
pinctrl-names = "i2c_active", "i2c_sleep";
|
||
|
|
pinctrl-0 = <&i2c_5_active>;
|
||
|
|
pinctrl-1 = <&i2c_5_sleep>;
|
||
|
|
qcom,noise-rjct-scl = <0>;
|
||
|
|
qcom,noise-rjct-sda = <0>;
|
||
|
|
qcom,bam-pipe-idx-cons = <12>;
|
||
|
|
qcom,bam-pipe-idx-prod = <13>;
|
||
|
|
qcom,master-id = <86>;
|
||
|
|
};
|
||
|
|
|
||
|
|
spi_5: spi@78b9000 { /* BLSP1 QUP5 */
|
||
|
|
compatible = "qcom,spi-qup-v2";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg-names = "spi_physical", "spi_bam_physical";
|
||
|
|
reg = <0x78b9000 0x1000>,
|
||
|
|
<0x7884000 0x23000>;
|
||
|
|
interrupt-names = "spi_irq", "spi_bam_irq";
|
||
|
|
interrupts = <0 99 0>, <0 238 0>;
|
||
|
|
spi-max-frequency = <18000000>;
|
||
|
|
qcom,use-pinctrl;
|
||
|
|
pinctrl-names = "spi_default", "spi_sleep";
|
||
|
|
pinctrl-0 = <&spi5_default &spi5_cs0_active>;
|
||
|
|
pinctrl-1 = <&spi5_sleep &spi5_cs0_sleep>;
|
||
|
|
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_blsp1_qup5_spi_apps_clk>;
|
||
|
|
clock-names = "iface_clk", "core_clk";
|
||
|
|
qcom,infinite-mode = <0>;
|
||
|
|
qcom,use-bam;
|
||
|
|
qcom,ver-reg-exists;
|
||
|
|
qcom,bam-consumer-pipe-index = <12>;
|
||
|
|
qcom,bam-producer-pipe-index = <13>;
|
||
|
|
qcom,master-id = <86>;
|
||
|
|
qcom,rt-priority;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spmi_bus: qcom,spmi@200f000 {
|
||
|
|
compatible = "qcom,spmi-pmic-arb";
|
||
|
|
reg = <0x200f000 0x1000>,
|
||
|
|
<0x2400000 0x400000>,
|
||
|
|
<0x2c00000 0x400000>,
|
||
|
|
<0x3800000 0x200000>,
|
||
|
|
<0x200a000 0x2100>;
|
||
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
||
|
|
interrupts = <0 190 0>;
|
||
|
|
qcom,pmic-arb-channel = <0>;
|
||
|
|
qcom,pmic-arb-ee = <0>;
|
||
|
|
#interrupt-cells = <3>;
|
||
|
|
interrupt-controller;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
cell-index = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,rmtfs_sharedmem@8e580000 {
|
||
|
|
compatible = "qcom,sharedmem-uio";
|
||
|
|
reg = <0x86700000 0x160000>;
|
||
|
|
reg-names = "rmtfs";
|
||
|
|
qcom,client-id = <0x00000001>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,dsp_sharedmem@8e6e0000 {
|
||
|
|
compatible = "qcom,sharedmem-uio";
|
||
|
|
reg = <0x867e0000 0x20000>;
|
||
|
|
reg-names = "rfsa_dsp";
|
||
|
|
qcom,client-id = <0x011013ec>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,mdm_sharedmem@8e6e0000 {
|
||
|
|
compatible = "qcom,sharedmem-uio";
|
||
|
|
reg = <0x867e0000 0x20000>;
|
||
|
|
reg-names = "rfsa_mdm";
|
||
|
|
qcom,client-id = <0x011013ed>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sdhc_1: sdhci@7824000 {
|
||
|
|
compatible = "qcom,sdhci-msm";
|
||
|
|
reg = <0x7824900 0x11c>, <0x7824000 0x800>;
|
||
|
|
reg-names = "hc_mem", "core_mem";
|
||
|
|
|
||
|
|
interrupts = <0 123 0>, <0 138 0>;
|
||
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
||
|
|
|
||
|
|
qcom,bus-width = <8>;
|
||
|
|
qcom,cpu-dma-latency-us = <701>;
|
||
|
|
qcom,msm-bus,name = "sdhc1";
|
||
|
|
qcom,msm-bus,num-cases = <8>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
|
||
|
|
<78 512 1600 3200>, /* 400 KB/s*/
|
||
|
|
<78 512 80000 160000>, /* 20 MB/s */
|
||
|
|
<78 512 100000 200000>, /* 25 MB/s */
|
||
|
|
<78 512 200000 400000>, /* 50 MB/s */
|
||
|
|
<78 512 400000 800000>, /* 100 MB/s */
|
||
|
|
<78 512 400000 800000>, /* 200 MB/s */
|
||
|
|
<78 512 2048000 4096000>; /* Max. bandwidth */
|
||
|
|
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
|
||
|
|
100000000 200000000 4294967295>;
|
||
|
|
|
||
|
|
clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_sdcc1_apps_clk>;
|
||
|
|
clock-names = "iface_clk", "core_clk";
|
||
|
|
|
||
|
|
qcom,clk-rates = <400000 25000000 50000000 100000000 177770000>;
|
||
|
|
qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sdhc_2: sdhci@7864000 {
|
||
|
|
compatible = "qcom,sdhci-msm";
|
||
|
|
reg = <0x7864900 0x11c>, <0x7864000 0x800>;
|
||
|
|
reg-names = "hc_mem", "core_mem";
|
||
|
|
|
||
|
|
interrupts = <0 125 0>, <0 221 0>;
|
||
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
||
|
|
|
||
|
|
qcom,bus-width = <4>;
|
||
|
|
qcom,cpu-dma-latency-us = <401>;
|
||
|
|
qcom,msm-bus,name = "sdhc2";
|
||
|
|
qcom,msm-bus,num-cases = <8>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
|
||
|
|
<81 512 1600 3200>, /* 400 KB/s*/
|
||
|
|
<81 512 80000 160000>, /* 20 MB/s */
|
||
|
|
<81 512 100000 200000>, /* 25 MB/s */
|
||
|
|
<81 512 200000 400000>, /* 50 MB/s */
|
||
|
|
<81 512 400000 800000>, /* 100 MB/s */
|
||
|
|
<81 512 400000 800000>, /* 200 MB/s */
|
||
|
|
<81 512 2048000 4096000>; /* Max. bandwidth */
|
||
|
|
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
|
||
|
|
100000000 200000000 4294967295>;
|
||
|
|
|
||
|
|
clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_sdcc2_apps_clk>;
|
||
|
|
clock-names = "iface_clk", "core_clk";
|
||
|
|
|
||
|
|
qcom,clk-rates = <400000 25000000 50000000 100000000 177770000>;
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-imem@8600000 {
|
||
|
|
compatible = "qcom,msm-imem";
|
||
|
|
reg = <0x08600000 0x1000>; /* Address and size of IMEM */
|
||
|
|
ranges = <0x0 0x08600000 0x1000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
|
||
|
|
mem_dump_table@10 {
|
||
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
||
|
|
reg = <0x10 8>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pil@94c {
|
||
|
|
compatible = "qcom,msm-imem-pil";
|
||
|
|
reg = <0x94c 200>;
|
||
|
|
};
|
||
|
|
|
||
|
|
restart_reason@65c {
|
||
|
|
compatible = "qcom,msm-imem-restart_reason";
|
||
|
|
reg = <0x65c 4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
boot_stats@6b0 {
|
||
|
|
compatible = "qcom,msm-imem-boot_stats";
|
||
|
|
reg = <0x6b0 32>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,mpm2-sleep-counter@4a3000 {
|
||
|
|
compatible = "qcom,mpm2-sleep-counter";
|
||
|
|
reg = <0x4a3000 0x1000>;
|
||
|
|
clock-frequency = <32768>;
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp1_uart1: serial@78af000 {
|
||
|
|
compatible = "qcom,msm-hsuart-v14";
|
||
|
|
reg = <0x78af000 0x200>,
|
||
|
|
<0x7884000 0x23000>;
|
||
|
|
reg-names = "core_mem", "bam_mem";
|
||
|
|
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
|
||
|
|
#address-cells = <0>;
|
||
|
|
interrupt-parent = <&blsp1_uart1>;
|
||
|
|
interrupts = <0 1 2>;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
interrupt-map-mask = <0xffffffff>;
|
||
|
|
interrupt-map = <0 &intc 0 107 0
|
||
|
|
1 &intc 0 238 0
|
||
|
|
2 &msm_gpio 1 0>;
|
||
|
|
qcom,bam-tx-ep-pipe-index = <0>;
|
||
|
|
qcom,bam-rx-ep-pipe-index = <1>;
|
||
|
|
clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,
|
||
|
|
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
|
||
|
|
clock-names = "core_clk", "iface_clk";
|
||
|
|
qcom,msm-bus,name = "blsp1_uart1";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<86 512 0 0>,
|
||
|
|
<86 512 500 800>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&hsuart_active>;
|
||
|
|
pinctrl-1 = <&hsuart_sleep>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,venus@1de0000 {
|
||
|
|
compatible = "qcom,pil-tz-generic";
|
||
|
|
reg = <0x1de0000 0x4000>;
|
||
|
|
|
||
|
|
vdd-supply = <&gdsc_venus>;
|
||
|
|
qcom,proxy-reg-names = "vdd";
|
||
|
|
clocks = <&clock_gcc clk_gcc_venus0_vcodec0_clk>,
|
||
|
|
<&clock_gcc clk_gcc_venus0_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_venus0_axi_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_axi_clk>,
|
||
|
|
<&clock_gcc clk_crypto_clk_src>;
|
||
|
|
|
||
|
|
clock-names = "core_clk", "iface_clk", "bus_clk",
|
||
|
|
"scm_core_clk", "scm_iface_clk", "scm_bus_clk",
|
||
|
|
"scm_core_clk_src";
|
||
|
|
qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk",
|
||
|
|
"scm_core_clk", "scm_iface_clk", "scm_bus_clk",
|
||
|
|
"scm_core_clk_src";
|
||
|
|
qcom,scm_core_clk_src = <80000000>;
|
||
|
|
|
||
|
|
qcom,pas-id = <9>;
|
||
|
|
qcom,proxy-timeout-ms = <5000>;
|
||
|
|
qcom,firmware-name = "venus";
|
||
|
|
linux,contiguous-region = <&venus_mem>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,mss@4080000 {
|
||
|
|
compatible = "qcom,pil-q6v56-mss";
|
||
|
|
reg = <0x04080000 0x100>,
|
||
|
|
<0x0194F000 0x010>,
|
||
|
|
<0x01950000 0x008>,
|
||
|
|
<0x01951000 0x008>,
|
||
|
|
<0x04020000 0x040>,
|
||
|
|
<0x01810000 0x004>;
|
||
|
|
reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc",
|
||
|
|
"rmb_base", "restart_reg_sec";
|
||
|
|
|
||
|
|
interrupts = <0 24 1>;
|
||
|
|
vdd_cx-supply = <&pm8916_s1_corner>;
|
||
|
|
vdd_cx-voltage = <7>;
|
||
|
|
vdd_mx-supply = <&pm8916_l3>;
|
||
|
|
vdd_mx-uV = <1050000>;
|
||
|
|
vdd_pll-supply = <&pm8916_l7>;
|
||
|
|
qcom,vdd_pll = <1800000>;
|
||
|
|
|
||
|
|
clocks = <&clock_rpm clk_xo_pil_mss_clk>,
|
||
|
|
<&clock_gcc clk_gcc_mss_cfg_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>,
|
||
|
|
<&clock_gcc clk_gcc_boot_rom_ahb_clk>;
|
||
|
|
clock-names = "xo", "iface_clk", "bus_clk", "mem_clk";
|
||
|
|
qcom,proxy-clock-names = "xo";
|
||
|
|
qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";
|
||
|
|
|
||
|
|
qcom,firmware-name = "modem";
|
||
|
|
qcom,pil-self-auth;
|
||
|
|
qcom,sysmon-id = <0>;
|
||
|
|
qcom,ssctl-instance-id = <0x12>;
|
||
|
|
|
||
|
|
/* GPIO inputs from mss */
|
||
|
|
qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
|
||
|
|
qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
|
||
|
|
qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
|
||
|
|
qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
|
||
|
|
qcom,gpio-ramdump-disable = <&smp2pgpio_ssr_smp2p_1_in 15 0>;
|
||
|
|
|
||
|
|
/* GPIO output to mss */
|
||
|
|
qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
|
||
|
|
linux,contiguous-region = <&modem_adsp_mem>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-pcm {
|
||
|
|
compatible = "qcom,msm-pcm-dsp";
|
||
|
|
qcom,msm-pcm-dsp-id = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-pcm-routing {
|
||
|
|
compatible = "qcom,msm-pcm-routing";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-pcm-low-latency {
|
||
|
|
compatible = "qcom,msm-pcm-dsp";
|
||
|
|
qcom,msm-pcm-dsp-id = <1>;
|
||
|
|
qcom,msm-pcm-low-latency;
|
||
|
|
qcom,latency-level = "ultra";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-pcm-lpa {
|
||
|
|
compatible = "qcom,msm-pcm-lpa";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-compress-dsp {
|
||
|
|
compatible = "qcom,msm-compress-dsp";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-voip-dsp {
|
||
|
|
compatible = "qcom,msm-voip-dsp";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-pcm-voice {
|
||
|
|
compatible = "qcom,msm-pcm-voice";
|
||
|
|
qcom,destroy-cvd;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-stub-codec {
|
||
|
|
compatible = "qcom,msm-stub-codec";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-fe {
|
||
|
|
compatible = "qcom,msm-dai-fe";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-pcm-afe {
|
||
|
|
compatible = "qcom,msm-pcm-afe";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-voice-svc {
|
||
|
|
compatible = "qcom,msm-voice-svc";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-pcm-loopback {
|
||
|
|
compatible = "qcom,msm-pcm-loopback";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-mi2s {
|
||
|
|
compatible = "qcom,msm-dai-mi2s";
|
||
|
|
qcom,msm-dai-q6-mi2s-prim {
|
||
|
|
compatible = "qcom,msm-dai-q6-mi2s";
|
||
|
|
qcom,msm-dai-q6-mi2s-dev-id = <0>;
|
||
|
|
qcom,msm-mi2s-rx-lines = <3>;
|
||
|
|
qcom,msm-mi2s-tx-lines = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-mi2s-sec {
|
||
|
|
compatible = "qcom,msm-dai-q6-mi2s";
|
||
|
|
qcom,msm-dai-q6-mi2s-dev-id = <1>;
|
||
|
|
qcom,msm-mi2s-rx-lines = <1>;
|
||
|
|
qcom,msm-mi2s-tx-lines = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-mi2s-tert {
|
||
|
|
compatible = "qcom,msm-dai-q6-mi2s";
|
||
|
|
qcom,msm-dai-q6-mi2s-dev-id = <2>;
|
||
|
|
qcom,msm-mi2s-rx-lines = <0>;
|
||
|
|
qcom,msm-mi2s-tx-lines = <3>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-mi2s-quat {
|
||
|
|
compatible = "qcom,msm-dai-q6-mi2s";
|
||
|
|
qcom,msm-dai-q6-mi2s-dev-id = <3>;
|
||
|
|
qcom,msm-mi2s-rx-lines = <1>;
|
||
|
|
qcom,msm-mi2s-tx-lines = <2>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-hdmi {
|
||
|
|
compatible = "qcom,msm-dai-q6-hdmi";
|
||
|
|
qcom,msm-dai-q6-dev-id = <8>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-lsm-client {
|
||
|
|
compatible = "qcom,msm-lsm-client";
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6 {
|
||
|
|
compatible = "qcom,msm-dai-q6";
|
||
|
|
qcom,msm-dai-q6-sb-0-rx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <16384>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-sb-0-tx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <16385>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-sb-1-rx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <16386>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-sb-1-tx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <16387>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-sb-3-rx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <16390>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-sb-3-tx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <16391>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-sb-4-rx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <16392>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-sb-4-tx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <16393>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-sb-5-tx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <16395>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-bt-sco-rx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <12288>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-bt-sco-tx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <12289>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-int-fm-rx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <12292>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-int-fm-tx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <12293>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-be-afe-pcm-rx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <224>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-be-afe-pcm-tx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <225>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-afe-proxy-rx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <241>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-afe-proxy-tx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <240>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-incall-record-rx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <32771>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-incall-record-tx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <32772>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-incall-music-rx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <32773>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-dai-q6-incall-music-2-rx {
|
||
|
|
compatible = "qcom,msm-dai-q6-dev";
|
||
|
|
qcom,msm-dai-q6-dev-id = <32770>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,msm-pcm-hostless {
|
||
|
|
compatible = "qcom,msm-pcm-hostless";
|
||
|
|
};
|
||
|
|
qcom,vidc@1d00000 {
|
||
|
|
compatible = "qcom,msm-vidc";
|
||
|
|
reg = <0x01d00000 0xff000>;
|
||
|
|
interrupts = <0 44 0>;
|
||
|
|
venus-supply = <&gdsc_venus>;
|
||
|
|
venus-core0-supply = <&gdsc_venus_core0>;
|
||
|
|
venus-core1-supply = <&gdsc_venus_core1>;
|
||
|
|
clocks = <&clock_gcc clk_gcc_venus0_vcodec0_clk>,
|
||
|
|
<&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>,
|
||
|
|
<&clock_gcc clk_gcc_venus0_core1_vcodec0_clk>,
|
||
|
|
<&clock_gcc clk_gcc_venus0_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_venus0_axi_clk>;
|
||
|
|
clock-names = "core_clk", "core0_clk", "core1_clk", "iface_clk", "bus_clk";
|
||
|
|
qcom,clock-configs = <0x1 0x0 0x0 0x0 0x0>;
|
||
|
|
qcom,sw-power-collapse;
|
||
|
|
qcom,load-freq-tbl =
|
||
|
|
<489600 266670000 0x0c000000>, /* HEVC decoder 1080p 60fps */
|
||
|
|
<489600 266670000 0x030fcfff>, /* Legacy decoder 1080p 60fps */
|
||
|
|
<489600 266670000 0x01000414>, /* Encoder turbo (wfd) */
|
||
|
|
<244800 133330000 0x0c000000>, /* HEVC decoder 1080p 30fps */
|
||
|
|
<244800 133330000 0x030ccfff>, /* Legacy decoder 1080p 30fps */
|
||
|
|
<244800 200000000 0x00030000>, /* VC1 decoder 1080p 30fps */
|
||
|
|
<244800 200000000 0x01000414>, /* Legacy encoder 1080p 30fps */
|
||
|
|
<220800 133330000 0x0c000000>, /* HEVC decoder 720p 60fps */
|
||
|
|
<220800 133330000 0x030fcfff>, /* Legacy decoder 720p 60fps */
|
||
|
|
<108000 133330000 0x0c000000>, /* HEVC decoder 720p 30fps */
|
||
|
|
<108000 133330000 0x030fcfff>, /* Legacy decoder 720p 30fps */
|
||
|
|
<108000 200000000 0x01000414>, /* Legacy encoder 720p 30fps */
|
||
|
|
<72000 133330000 0x0c000000>, /* HEVC decoder VGA 60fps */
|
||
|
|
<72000 133330000 0x030fcfff>, /* Legacy decoder VGA 60fps */
|
||
|
|
<36000 133330000 0x0c000000>, /* HEVC VGA 30 fps */
|
||
|
|
<36000 133330000 0x030fcfff>, /* Legacy decoder VGA 30 fps */
|
||
|
|
<36000 133330000 0x01000414>; /* Legacy encoder VGA 30 fps */
|
||
|
|
|
||
|
|
qcom,hfi = "venus";
|
||
|
|
qcom,reg-presets = <0xE0020 0x0aaaaaaa>,
|
||
|
|
<0xE0024 0x0aaaaaaa>,
|
||
|
|
<0x80124 0x00000003>;
|
||
|
|
qcom,qdss-presets = <0x825000 0x1000>,
|
||
|
|
<0x826000 0x1000>,
|
||
|
|
<0x821000 0x1000>,
|
||
|
|
<0x802000 0x1000>,
|
||
|
|
<0x9180000 0x1000>,
|
||
|
|
<0x9181000 0x1000>;
|
||
|
|
qcom,max-hw-load = <489600>; /* 1080p @ 30 + 1080p @ 30 */
|
||
|
|
qcom,enable-idle-indicator;
|
||
|
|
qcom,vidc-iommu-domains {
|
||
|
|
qcom,domain-ns {
|
||
|
|
qcom,vidc-domain-phandle = <&venus_domain_ns>;
|
||
|
|
qcom,vidc-partition-buffer-types = <0x7ff>,
|
||
|
|
<0x800>;
|
||
|
|
};
|
||
|
|
qcom,domain-sec-bs {
|
||
|
|
qcom,vidc-domain-phandle = <&venus_domain_sec_bitstream>;
|
||
|
|
qcom,vidc-partition-buffer-types = <0x241>;
|
||
|
|
};
|
||
|
|
qcom,domain-sec-px {
|
||
|
|
qcom,vidc-domain-phandle = <&venus_domain_sec_pixel>;
|
||
|
|
qcom,vidc-partition-buffer-types = <0x106>;
|
||
|
|
};
|
||
|
|
qcom,domain-sec-np {
|
||
|
|
qcom,vidc-domain-phandle = <&venus_domain_sec_non_pixel>;
|
||
|
|
qcom,vidc-partition-buffer-types = <0x480>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
qcom,msm-bus-clients {
|
||
|
|
qcom,msm-bus-client@0 {
|
||
|
|
qcom,msm-bus,name = "venc-ddr";
|
||
|
|
qcom,msm-bus,num-cases = <6>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<63 512 0 0>,
|
||
|
|
<63 512 136806 1236684>, /* VGA 30 fps */
|
||
|
|
<63 512 410521 1859686>, /* VGA 60 fps */
|
||
|
|
<63 512 410521 1859686>, /* 720p 30 fps */
|
||
|
|
<63 512 930406 1859686>, /* 720p 60 fps */
|
||
|
|
<63 512 930406 1859686>; /* 1080p 30 fps */
|
||
|
|
qcom,bus-configs = <0x01000414>;
|
||
|
|
};
|
||
|
|
qcom,msm-bus-client@1 {
|
||
|
|
qcom,msm-bus,name = "vdec-core0-ddr";
|
||
|
|
qcom,msm-bus,num-cases = <7>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<63 512 0 0>,
|
||
|
|
<63 512 101991 644403>,
|
||
|
|
<63 512 204083 1288704>,
|
||
|
|
<63 512 306074 644403>,
|
||
|
|
<63 512 612250 1288704>,
|
||
|
|
<63 512 693863 644403>,
|
||
|
|
<63 512 1387725 2577408>;
|
||
|
|
qcom,bus-configs = <0x030fcfff>;
|
||
|
|
};
|
||
|
|
qcom,msm-bus-client@2 {
|
||
|
|
qcom,msm-bus,name = "vdec-core1-ddr";
|
||
|
|
qcom,msm-bus,num-cases = <7>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<63 512 0 0>,
|
||
|
|
<63 512 96051 572826>,
|
||
|
|
<63 512 192103 1145754>,
|
||
|
|
<63 512 288256 572826>,
|
||
|
|
<63 512 576410 1145754>,
|
||
|
|
<63 512 653312 572826>,
|
||
|
|
<63 512 1306624 2291405>;
|
||
|
|
qcom,bus-configs = <0x0c000000>;
|
||
|
|
};
|
||
|
|
qcom,msm-bus-client@3 {
|
||
|
|
qcom,msm-bus,name = "venus-arm9-ddr";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<63 512 0 0>,
|
||
|
|
<63 512 1000 1000>;
|
||
|
|
qcom,bus-configs = <0x00000000>;
|
||
|
|
qcom,bus-passive;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,pronto@a21b000 {
|
||
|
|
compatible = "qcom,pil-tz-generic";
|
||
|
|
reg = <0x0a21b000 0x3000>;
|
||
|
|
interrupts = <0 149 1>;
|
||
|
|
|
||
|
|
vdd_pronto_pll-supply = <&pm8916_l7>;
|
||
|
|
proxy-reg-names = "vdd_pronto_pll";
|
||
|
|
vdd_pronto_pll-uV-uA = <1800000 18000>;
|
||
|
|
clocks = <&clock_rpm clk_xo_pil_pronto_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_axi_clk>,
|
||
|
|
<&clock_gcc clk_crypto_clk_src>;
|
||
|
|
|
||
|
|
clock-names = "xo", "scm_core_clk", "scm_iface_clk",
|
||
|
|
"scm_bus_clk", "scm_core_clk_src";
|
||
|
|
qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
|
||
|
|
"scm_bus_clk", "scm_core_clk_src";
|
||
|
|
qcom,scm_core_clk_src = <80000000>;
|
||
|
|
|
||
|
|
qcom,pas-id = <6>;
|
||
|
|
qcom,proxy-timeout-ms = <10000>;
|
||
|
|
qcom,smem-id = <422>;
|
||
|
|
qcom,sysmon-id = <6>;
|
||
|
|
qcom,ssctl-instance-id = <0x13>;
|
||
|
|
qcom,firmware-name = "wcnss";
|
||
|
|
|
||
|
|
/* GPIO inputs from wcnss */
|
||
|
|
qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>;
|
||
|
|
qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>;
|
||
|
|
qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>;
|
||
|
|
qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_4_in 3 0>;
|
||
|
|
|
||
|
|
/* GPIO output to wcnss */
|
||
|
|
qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>;
|
||
|
|
linux,contiguous-region = <&peripheral_mem>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,avtimer@7706000 {
|
||
|
|
compatible = "qcom,avtimer";
|
||
|
|
reg = <0x0770600C 0x4>,
|
||
|
|
<0x07706010 0x4>;
|
||
|
|
reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
|
||
|
|
qcom,clk_div = <27>;
|
||
|
|
};
|
||
|
|
|
||
|
|
mcd {
|
||
|
|
compatible = "qcom,mcd";
|
||
|
|
qcom,ce-hw-instance = <0>;
|
||
|
|
qcom,ce-device = <0>;
|
||
|
|
clocks = <&clock_gcc clk_crypto_clk_src>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_crypto_axi_clk>;
|
||
|
|
clock-names = "core_clk_src", "core_clk",
|
||
|
|
"iface_clk", "bus_clk";
|
||
|
|
qcom,ce-opp-freq = <100000000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&gdsc_venus {
|
||
|
|
clock-names = "bus_clk", "core_clk";
|
||
|
|
clocks = <&clock_gcc clk_gcc_venus0_axi_clk>,
|
||
|
|
<&clock_gcc clk_gcc_venus0_vcodec0_clk>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&gdsc_mdss {
|
||
|
|
clock-names = "core_clk", "bus_clk";
|
||
|
|
clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,
|
||
|
|
<&clock_gcc clk_gcc_mdss_axi_clk>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&gdsc_jpeg {
|
||
|
|
clock-names = "core_clk", "bus_clk";
|
||
|
|
clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_jpeg_axi_clk>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&gdsc_vfe {
|
||
|
|
clock-names = "core_clk", "bus_clk", "micro_clk",
|
||
|
|
"cpp_clk", "csi_clk";
|
||
|
|
clocks = <&clock_gcc clk_gcc_camss_vfe0_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_vfe_axi_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_micro_ahb_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_cpp_clk>,
|
||
|
|
<&clock_gcc clk_gcc_camss_csi_vfe0_clk>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&gdsc_oxili_gx {
|
||
|
|
clock-names = "core_root_clk", "core_clk", "gmem_clk";
|
||
|
|
clocks = <&clock_gcc clk_gfx3d_clk_src>,
|
||
|
|
<&clock_gcc clk_gcc_oxili_gfx3d_clk>,
|
||
|
|
<&clock_gcc clk_gcc_oxili_gmem_clk>;
|
||
|
|
qcom,enable-root-clk;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&gdsc_venus_core0 {
|
||
|
|
qcom,support-hw-trigger;
|
||
|
|
clock-names ="core0_clk";
|
||
|
|
clocks = <&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&gdsc_venus_core1 {
|
||
|
|
qcom,support-hw-trigger;
|
||
|
|
clock-names ="core1_clk";
|
||
|
|
clocks = <&clock_gcc clk_gcc_venus0_core1_vcodec0_clk>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
#include "msm-pm8916-rpm-regulator.dtsi"
|
||
|
|
#include "msm-pm8916.dtsi"
|
||
|
|
#include "msm8939-regulator.dtsi"
|
||
|
|
|
||
|
|
&pm8916_vadc {
|
||
|
|
chan@0 {
|
||
|
|
label = "usb_in";
|
||
|
|
reg = <0>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <7>;
|
||
|
|
qcom,calibration-type = "absolute";
|
||
|
|
qcom,scale-function = <0>;
|
||
|
|
qcom,hw-settle-time = <0>;
|
||
|
|
qcom,fast-avg-setup = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
chan@2 {
|
||
|
|
label = "ireg_fb";
|
||
|
|
reg = <2>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <6>;
|
||
|
|
qcom,calibration-type = "absolute";
|
||
|
|
qcom,scale-function = <0>;
|
||
|
|
qcom,hw-settle-time = <0>;
|
||
|
|
qcom,fast-avg-setup = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
chan@5 {
|
||
|
|
label = "vcoin";
|
||
|
|
reg = <5>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <1>;
|
||
|
|
qcom,calibration-type = "absolute";
|
||
|
|
qcom,scale-function = <0>;
|
||
|
|
qcom,hw-settle-time = <0>;
|
||
|
|
qcom,fast-avg-setup = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
chan@6 {
|
||
|
|
label = "vbat_sns";
|
||
|
|
reg = <6>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <1>;
|
||
|
|
qcom,calibration-type = "absolute";
|
||
|
|
qcom,scale-function = <0>;
|
||
|
|
qcom,hw-settle-time = <0>;
|
||
|
|
qcom,fast-avg-setup = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
chan@7 {
|
||
|
|
label = "vph_pwr";
|
||
|
|
reg = <7>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <1>;
|
||
|
|
qcom,calibration-type = "absolute";
|
||
|
|
qcom,scale-function = <0>;
|
||
|
|
qcom,hw-settle-time = <0>;
|
||
|
|
qcom,fast-avg-setup = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
chan@b {
|
||
|
|
label = "chg_temp";
|
||
|
|
reg = <0xb>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <0>;
|
||
|
|
qcom,calibration-type = "absolute";
|
||
|
|
qcom,scale-function = <3>;
|
||
|
|
qcom,hw-settle-time = <0>;
|
||
|
|
qcom,fast-avg-setup = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
chan@30 {
|
||
|
|
label = "batt_therm";
|
||
|
|
reg = <0x30>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <0>;
|
||
|
|
qcom,calibration-type = "ratiometric";
|
||
|
|
qcom,scale-function = <1>;
|
||
|
|
qcom,hw-settle-time = <0xb>;
|
||
|
|
qcom,fast-avg-setup = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
chan@31 {
|
||
|
|
label = "batt_id";
|
||
|
|
reg = <0x31>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <0>;
|
||
|
|
qcom,calibration-type = "ratiometric";
|
||
|
|
qcom,scale-function = <0>;
|
||
|
|
qcom,hw-settle-time = <0xb>;
|
||
|
|
qcom,fast-avg-setup = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
chan@36 {
|
||
|
|
label = "pa_therm0";
|
||
|
|
reg = <0x36>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <0>;
|
||
|
|
qcom,calibration-type = "ratiometric";
|
||
|
|
qcom,scale-function = <2>;
|
||
|
|
qcom,hw-settle-time = <2>;
|
||
|
|
qcom,fast-avg-setup = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
chan@32 {
|
||
|
|
label = "xo_therm";
|
||
|
|
reg = <0x32>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <0>;
|
||
|
|
qcom,calibration-type = "ratiometric";
|
||
|
|
qcom,scale-function = <4>;
|
||
|
|
qcom,hw-settle-time = <2>;
|
||
|
|
qcom,fast-avg-setup = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
chan@3c {
|
||
|
|
label = "xo_therm_buf";
|
||
|
|
reg = <0x3c>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <0>;
|
||
|
|
qcom,calibration-type = "ratiometric";
|
||
|
|
qcom,scale-function = <4>;
|
||
|
|
qcom,hw-settle-time = <2>;
|
||
|
|
qcom,fast-avg-setup = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&pm8916_adc_tm {
|
||
|
|
/* Channel Node */
|
||
|
|
chan@30 {
|
||
|
|
label = "batt_therm";
|
||
|
|
reg = <0x30>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <0>;
|
||
|
|
qcom,calibration-type = "ratiometric";
|
||
|
|
qcom,scale-function = <1>;
|
||
|
|
qcom,hw-settle-time = <0xb>;
|
||
|
|
qcom,fast-avg-setup = <2>;
|
||
|
|
qcom,btm-channel-number = <0x48>;
|
||
|
|
};
|
||
|
|
|
||
|
|
chan@6 {
|
||
|
|
label = "vbat_sns";
|
||
|
|
reg = <0x6>;
|
||
|
|
qcom,decimation = <0>;
|
||
|
|
qcom,pre-div-channel-scaling = <1>;
|
||
|
|
qcom,calibration-type = "absolute";
|
||
|
|
qcom,scale-function = <0>;
|
||
|
|
qcom,hw-settle-time = <0xb>;
|
||
|
|
qcom,fast-avg-setup = <2>;
|
||
|
|
qcom,btm-channel-number = <0x68>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
#include "msm8939-gpu.dtsi"
|