373 lines
11 KiB
Plaintext
373 lines
11 KiB
Plaintext
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/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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mdss_mdp: qcom,mdss_mdp@1a00000 {
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compatible = "qcom,mdss_mdp";
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reg = <0x01a00000 0x90000>,
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<0x01ab0000 0x1040>;
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reg-names = "mdp_phys", "vbif_phys";
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interrupts = <0 72 0>;
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vdd-supply = <&gdsc_mdss>;
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/* Bus Scale Settings */
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qcom,msm-bus,name = "mdss_mdp";
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<22 512 0 0>,
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<22 512 0 6400000>,
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<22 512 0 6400000>;
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/* Fudge factors */
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qcom,mdss-ab-factor = <1 1>; /* 1 time */
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qcom,mdss-ib-factor = <1 1>; /* 1 time */
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qcom,mdss-clk-factor = <105 100>; /* 1.05 times */
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qcom,max-mixer-width = <2048>;
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qcom,max-pipe-width = <2048>;
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/* VBIF QoS remapper settings*/
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qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>;
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qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>;
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qcom,mdss-has-panic-ctrl;
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qcom,mdss-per-pipe-panic-luts = <0x000f>,
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<0xffff>,
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<0xfffc>,
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<0xff00>;
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qcom,mdss-mdp-reg-offset = <0x00001000>;
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qcom,max-bandwidth-low-kbps = <4000000>;
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qcom,max-bandwidth-high-kbps = <4000000>;
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qcom,max-bandwidth-per-pipe-kbps = <2300000>;
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/* Bandwidth limit settings */
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qcom,max-bw-settings = <1 4000000>, /* Default */
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<2 2300000>; /* Camera */
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qcom,max-clk-rate = <320000000>;
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qcom,mdss-default-ot-rd-limit = <32>;
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qcom,mdss-default-ot-wr-limit = <16>;
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qcom,mdss-pipe-vig-off = <0x00005000>;
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qcom,mdss-pipe-rgb-off = <0x00015000 0x00017000>;
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qcom,mdss-pipe-dma-off = <0x00025000>;
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qcom,mdss-pipe-cursor-off = <0x00035000>;
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qcom,mdss-pipe-vig-xin-id = <0>;
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qcom,mdss-pipe-rgb-xin-id = <1 5>;
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qcom,mdss-pipe-dma-xin-id = <2>;
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qcom,mdss-pipe-cursor-xin-id = <7>;
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/* Offsets relative to "mdp_phys + mdp-reg-offset" address */
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qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2AC 0 0>;
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qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x2AC 4 8>,
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<0x2B4 4 8>;
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qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>;
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qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3A8 16 15>;
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qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400>;
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qcom,mdss-mixer-intf-off = <0x00045000 0x00046000>;
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qcom,mdss-dspp-off = <0x00055000>;
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qcom,mdss-wb-off = <0x00065000 0x00066000>;
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qcom,mdss-intf-off = <0x00000000 0x0006B800 0x0006C000>;
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qcom,mdss-pingpong-off = <0x00071000 0x00071800>;
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qcom,mdss-slave-pingpong-off = <0x00073000>;
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qcom,mdss-cdm-off = <0x0007a200>;
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qcom,mdss-wfd-mode = "intf";
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qcom,mdss-highest-bank-bit = <0x1>;
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qcom,mdss-has-decimation;
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qcom,mdss-has-non-scalar-rgb;
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qcom,mdss-has-rotator-downscale;
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qcom,mdss-idle-power-collapse-enabled;
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qcom,mdss-rot-block-size = <64>;
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clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>,
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<&clock_gcc clk_gcc_mdss_axi_clk>,
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<&clock_gcc clk_mdp_clk_src>,
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<&clock_gcc_mdss clk_mdss_mdp_vote_clk>,
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<&clock_gcc clk_gcc_mdss_vsync_clk>;
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clock-names = "iface_clk", "bus_clk", "core_clk_src",
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"core_clk", "vsync_clk";
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qcom,mdp-settings = <0x01190 0x00000000>,
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<0x0506c 0x00000000>,
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<0x1506c 0x00000000>,
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<0x1706c 0x00000000>,
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<0x2506c 0x00000000>;
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qcom,regs-dump-mdp = <0x01000 0x01454>,
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<0x02000 0x02064>,
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<0x02200 0x02264>,
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<0x02400 0x02464>,
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<0x05000 0x05150>,
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<0x05200 0x05230>,
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<0x15000 0x15150>,
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<0x17000 0x17150>,
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<0x25000 0x25150>,
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<0x35000 0x35150>,
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<0x45000 0x452bc>,
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<0x46000 0x462bc>,
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<0x55000 0x5522c>,
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<0x65000 0x652c0>,
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<0x66000 0x662c0>,
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<0x6b800 0x6ba68>,
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<0x6c000 0x6c268>,
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<0x71000 0x710d4>,
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<0x71800 0x718d4>;
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qcom,regs-dump-names-mdp = "MDP",
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"CTL_0", "CTL_1", "CTL_2",
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"VIG0_SSPP", "VIG0",
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"RGB0_SSPP", "RGB1_SSPP",
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"DMA0_SSPP",
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"CURSOR0_SSPP",
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"LAYER_0", "LAYER_1",
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"DSPP_0",
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"WB_0", "WB_2",
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"INTF_1", "INTF_2",
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"PP_0", "PP_1";
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/* buffer parameters to calculate prefill bandwidth */
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qcom,mdss-prefill-outstanding-buffer-bytes = <0>;
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qcom,mdss-prefill-y-buffer-bytes = <0>;
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qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>;
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qcom,mdss-prefill-scaler-buffer-lines-caf = <4>;
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qcom,mdss-prefill-post-scaler-buffer-pixels = <2048>;
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qcom,mdss-prefill-pingpong-buffer-pixels = <4096>;
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qcom,mdss-pp-offsets {
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qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>;
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qcom,mdss-sspp-vig-pcc-off = <0x1780>;
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qcom,mdss-sspp-rgb-pcc-off = <0x380>;
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qcom,mdss-sspp-dma-pcc-off = <0x380>;
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qcom,mdss-lm-pgc-off = <0x3C0>;
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qcom,mdss-dspp-pcc-off = <0x1700>;
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qcom,mdss-dspp-pgc-off = <0x17C0>;
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};
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smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb {
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compatible = "qcom,smmu_mdp_unsec";
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};
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smmu_mdp_sec: qcom,smmu_mdp_sec_cb {
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compatible = "qcom,smmu_mdp_sec";
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};
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mdss_fb0: qcom,mdss_fb_primary {
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cell-index = <0>;
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compatible = "qcom,mdss-fb";
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qcom,cont-splash-memory {
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linux,contiguous-region = <&cont_splash_mem>;
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};
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};
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mdss_fb1: qcom,mdss_fb_wfd {
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cell-index = <1>;
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compatible = "qcom,mdss-fb";
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};
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mdss_fb2: qcom,mdss_fb_secondary {
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cell-index = <2>;
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compatible = "qcom,mdss-fb";
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};
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};
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mdss_dsi: qcom,mdss_dsi@0 {
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compatible = "qcom,mdss-dsi";
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hw-config = "single_dsi";
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#address-cells = <1>;
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#size-cells = <1>;
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gdsc-supply = <&gdsc_mdss>;
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vdda-supply = <&pm8937_l2>;
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vddio-supply = <&pm8937_l6>;
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/* Bus Scale Settings */
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qcom,msm-bus,name = "mdss_dsi";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<22 512 0 0>,
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<22 512 0 1000>;
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ranges = <0x1a94000 0x1a94000 0x300
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0x1a94400 0x1a94400 0x280
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0x1a94b80 0x1a94b80 0x30
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0x193e000 0x193e000 0x30
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0x1a96000 0x1a96000 0x300
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0x1a96400 0x1a96400 0x280
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0x1a96b80 0x1a96b80 0x30
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0x193e000 0x193e000 0x30>;
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clocks = <&clock_gcc_mdss clk_mdss_mdp_vote_clk>,
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<&clock_gcc clk_gcc_mdss_ahb_clk>,
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<&clock_gcc clk_gcc_mdss_axi_clk>,
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<&clock_gcc_mdss clk_ext_byte0_clk_src>,
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<&clock_gcc_mdss clk_ext_byte1_clk_src>,
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<&clock_gcc_mdss clk_ext_pclk0_clk_src>,
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<&clock_gcc_mdss clk_ext_pclk1_clk_src>;
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clock-names = "mdp_core_clk", "iface_clk", "bus_clk",
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"ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk",
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"ext_pixel1_clk";
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qcom,mmss-ulp-clamp-ctrl-offset = <0x20>;
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qcom,mmss-phyreset-ctrl-offset = <0x24>;
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qcom,mdss-fb-map-prim = <&mdss_fb0>;
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qcom,mdss-fb-map-sec = <&mdss_fb2>;
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qcom,core-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,core-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "gdsc";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1200000>;
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qcom,supply-enable-load = <100000>;
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qcom,supply-disable-load = <100>;
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qcom,supply-post-on-sleep = <20>;
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};
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};
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qcom,phy-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,phy-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vddio";
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qcom,supply-min-voltage = <1800000>;
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qcom,supply-max-voltage = <1800000>;
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qcom,supply-enable-load = <100000>;
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qcom,supply-disable-load = <100>;
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};
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};
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mdss_dsi0: qcom,mdss_dsi_ctrl0@1a94000 {
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compatible = "qcom,mdss-dsi-ctrl";
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label = "MDSS DSI CTRL->0";
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cell-index = <0>;
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reg = <0x1a94000 0x300>,
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<0x1a94400 0x280>,
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<0x1a94b80 0x30>,
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<0x193e000 0x30>;
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reg-names = "dsi_ctrl", "dsi_phy",
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"dsi_phy_regulator", "mmss_misc_phys";
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qcom,timing-db-mode;
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qcom,mdss-mdp = <&mdss_mdp>;
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vdd-supply = <&pm8937_l17>;
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vddio-supply = <&pm8937_l6>;
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clocks = <&clock_gcc_mdss clk_gcc_mdss_byte0_clk>,
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<&clock_gcc_mdss clk_gcc_mdss_pclk0_clk>,
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<&clock_gcc clk_gcc_mdss_esc0_clk>,
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<&clock_gcc_mdss clk_byte0_clk_src>,
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<&clock_gcc_mdss clk_pclk0_clk_src>;
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clock-names = "byte_clk", "pixel_clk", "core_clk",
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"byte_clk_rcg", "pixel_clk_rcg";
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qcom,platform-strength-ctrl = [ff 06];
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qcom,platform-bist-ctrl = [00 00 b1 ff 00 00];
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qcom,platform-regulator-settings = [03 08 07 00
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20 07 01];
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qcom,platform-lane-config = [01 c0 00 00 00 00 00 01 97
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01 c0 00 00 05 00 00 01 97
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01 c0 00 00 0a 00 00 01 97
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01 c0 00 00 0f 00 00 01 97
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00 40 00 00 00 00 00 01 ff];
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};
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mdss_dsi1: qcom,mdss_dsi_ctrl1@1a96000 {
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compatible = "qcom,mdss-dsi-ctrl";
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label = "MDSS DSI CTRL->1";
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cell-index = <1>;
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reg = <0x1a96000 0x300>,
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<0x1a96400 0x280>,
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<0x1a94b80 0x30>,
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<0x193e000 0x30>;
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reg-names = "dsi_ctrl", "dsi_phy",
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"dsi_phy_regulator", "mmss_misc_phys";
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qcom,mdss-mdp = <&mdss_mdp>;
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vdd-supply = <&pm8937_l17>;
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vddio-supply = <&pm8937_l6>;
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clocks = <&clock_gcc_mdss clk_gcc_mdss_byte1_clk>,
|
||
|
|
<&clock_gcc_mdss clk_gcc_mdss_pclk1_clk>,
|
||
|
|
<&clock_gcc clk_gcc_mdss_esc1_clk>,
|
||
|
|
<&clock_gcc_mdss clk_byte1_clk_src>,
|
||
|
|
<&clock_gcc_mdss clk_pclk1_clk_src>;
|
||
|
|
clock-names = "byte_clk", "pixel_clk", "core_clk",
|
||
|
|
"byte_clk_rcg", "pixel_clk_rcg";
|
||
|
|
|
||
|
|
qcom,platform-strength-ctrl = [ff 06];
|
||
|
|
qcom,platform-bist-ctrl = [00 00 b1 ff 00 00];
|
||
|
|
qcom,platform-regulator-settings = [03 08 07 00
|
||
|
|
20 07 01];
|
||
|
|
qcom,platform-lane-config = [01 c0 00 00 00 00 00 01 97
|
||
|
|
01 c0 00 00 05 00 00 01 97
|
||
|
|
01 c0 00 00 0a 00 00 01 97
|
||
|
|
01 c0 00 00 0f 00 00 01 97
|
||
|
|
00 40 00 00 00 00 00 01 ff];
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,mdss_wb_panel {
|
||
|
|
compatible = "qcom,mdss_wb";
|
||
|
|
qcom,mdss_pan_res = <640 640>;
|
||
|
|
qcom,mdss_pan_bpp = <24>;
|
||
|
|
qcom,mdss-fb-map = <&mdss_fb1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
mdss_rotator: qcom,mdss_rotator {
|
||
|
|
compatible = "qcom,mdss_rotator";
|
||
|
|
qcom,mdss-wb-count = <1>;
|
||
|
|
qcom,mdss-has-downscale;
|
||
|
|
qcom,mdss-has-ubwc;
|
||
|
|
/* Bus Scale Settings */
|
||
|
|
qcom,msm-bus,name = "mdss_rotator";
|
||
|
|
qcom,msm-bus,num-cases = <3>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<22 512 0 0>,
|
||
|
|
<22 512 0 6400000>,
|
||
|
|
<22 512 0 6400000>;
|
||
|
|
|
||
|
|
rot-vdd-supply = <&gdsc_mdss>;
|
||
|
|
qcom,supply-names = "rot-vdd";
|
||
|
|
|
||
|
|
clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>,
|
||
|
|
<&clock_gcc_mdss clk_mdss_rotator_vote_clk>;
|
||
|
|
clock-names = "iface_clk", "rot_core_clk";
|
||
|
|
|
||
|
|
};
|
||
|
|
};
|